SaltForTheThirsty

atxmega32e5 Registers()

Home

Projects

Lessons

xMega

Registers and bits for the atxmega32e5

Updated 9/13/2022

0x0000 GPIO General Purpose IO Registers

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	GPIOR0	GPIOR0[7:0]
0x0001	GPIOR1	GPIOR1[7:0]
0x0002	GPIOR2	GPIOR2[7:0]
0x0003	GPIOR3	GPIOR3[7:0]
0x0004	Reserved	-	-	-	-	-	-	-	-
0x0005	Reserved	-	-	-	-	-	-	-	-
0x0006	Reserved	-	-	-	-	-	-	-	-
0x0007	Reserved	-	-	-	-	-	-	-	-
0x0008	Reserved	-	-	-	-	-	-	-	-
0x0009	Reserved	-	-	-	-	-	-	-	-
0x000A	Reserved	-	-	-	-	-	-	-	-
0x000B	Reserved	-	-	-	-	-	-	-	-
0x000C	Reserved	-	-	-	-	-	-	-	-
0x000D	Reserved	-	-	-	-	-	-	-	-
0x000E	Reserved	-	-	-	-	-	-	-	-
0x000F	Reserved	-	-	-	-	-	-	-	-

Aliases

            
        ;*************************************************************************
        ;** VPORT0 - Virtual Ports
        ;*************************************************************************

        .equ VPORT0_DIR = 16		// I/O Port Data Direction
        .equ VPORT0_OUT = 17		// I/O Port Output
        .equ VPORT0_IN = 18		// I/O Port Input
        .equ VPORT0_INTFLAGS = 19		// Interrupt Flag Register

0x0010 VPORT0 Virtual Port A

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	DIR	DIR[7:0]
0x0001	OUT	OUT[7:0]
0x0002	IN	IN[7:0]
0x0003	INTFLAGS	INT7IF	INT6IF	INT5IF	INT4IF	INT3IF	INT2IF	INT1IF	INT0IF

Aliases

            
        ;*************************************************************************
        ;** VPORT1 - Virtual Ports
        ;*************************************************************************
        
        .equ VPORT1_DIR = 20		// I/O Port Data Direction
        .equ VPORT1_OUT = 21		// I/O Port Output
        .equ VPORT1_IN = 22		// I/O Port Input
        .equ VPORT1_INTFLAGS = 23		// Interrupt Flag Register

0x0014 VPORT1 Virtual Port C

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	DIR	DIR[7:0]
0x0001	OUT	OUT[7:0]
0x0002	IN	IN[7:0]
0x0003	INTFLAGS	INT7IF	INT6IF	INT5IF	INT4IF	INT3IF	INT2IF	INT1IF	INT0IF

Aliases

            
        ;*************************************************************************
        ;** VPORT2 - Virtual Ports
        ;*************************************************************************
        
        .equ VPORT2_DIR = 24		// I/O Port Data Direction
        .equ VPORT2_OUT = 25		// I/O Port Output
        .equ VPORT2_IN = 26		// I/O Port Input
        .equ VPORT2_INTFLAGS = 27		// Interrupt Flag Register

0x0018 VPORT2 Virtual Port D

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	DIR	DIR[7:0]
0x0001	OUT	OUT[7:0]
0x0002	IN	IN[7:0]
0x0003	INTFLAGS	INT7IF	INT6IF	INT5IF	INT4IF	INT3IF	INT2IF	INT1IF	INT0IF

Aliases

            
            ;*************************************************************************
            ;** VPORT3 - Virtual Ports
            ;*************************************************************************
            
            .equ VPORT3_DIR = 28		// I/O Port Data Direction
            .equ VPORT3_OUT = 29		// I/O Port Output
            .equ VPORT3_IN = 30		// I/O Port Input
            .equ VPORT3_INTFLAGS = 31		// Interrupt Flag Register

0x001C VPORT3 Virtual Port R

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	DIR	DIR[7:0]
0x0001	OUT	OUT[7:0]
0x0002	IN	IN[7:0]
0x0003	INTFLAGS	INT7IF	INT6IF	INT5IF	INT4IF	INT3IF	INT2IF	INT1IF	INT0IF

cbi, sbi, sbic, and sbis does not work with registers below here

0x0030 CPU CPU

Aliases

        
        .equ CCP_SPM_gc = (0x9D<<0) ; SPM Instruction Protection
        .equ CCP_IOREG_gc = (0xD8<<00) ; IO Register Protection 
        .equ CPU_CCP = 52

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	Reserved	-	-	-	-	-	-	-	-
0x0001	Reserved	-	-	-	-	-	-	-	-
0x0002	Reserved	-	-	-	-	-	-	-	-
0x0003	Reserved	-	-	-	-	-	-	-	-
0x0004	CCP	CCP[7:0]
0x0005	Reserved	-	-	-	-	-	-	-	-
0x0006	Reserved	-	-	-	-	-	-	-	-
0x0007	Reserved	-	-	-	-	-	-	-	-
0x0008	RAMPD	RAMPD[7:0]
0x0009	RAMPX	RAMPX[7:0]
0x000A	RAMPY	RAMPY[7:0]
0x000B	RAMPZ	RAMPZ[7:0]
0x000C	EIND	EIND[7:0]
0x000D	SPL	SPL[7:0]
0x000E	SPH	SPH[7:0]
0x000F	SREG	I	T	H	S	V	N	Z	C

in and out does not work with registers below here

0x0040 CLK Clock Control

Aliases

        
        ;*************************************************************************
        ;** CLK - Clock System
        ;*************************************************************************
        
        ; CLK_CTRL masks
        .equ CLK_SCLKSEL_gm = 0x07 ; System Clock Selection group mask
        .equ CLK_SCLKSEL_gp = 0 ; System Clock Selection group position
        .equ CLK_SCLKSEL0_bm = (1<<0) ; System Clock Selection bit 0 mask
        .equ CLK_SCLKSEL0_bp = 0 ; System Clock Selection bit 0 position
        .equ CLK_SCLKSEL1_bm = (1<<1) ; System Clock Selection bit 1 mask
        .equ CLK_SCLKSEL1_bp = 1 ; System Clock Selection bit 1 position
        .equ CLK_SCLKSEL2_bm = (1<<2) ; System Clock Selection bit 2 mask
        .equ CLK_SCLKSEL2_bp = 2 ; System Clock Selection bit 2 position
        
        ; CLK_PSCTRL masks
        .equ CLK_PSADIV_gm = 0x7C ; Prescaler A Division Factor group mask
        .equ CLK_PSADIV_gp = 2 ; Prescaler A Division Factor group position
        .equ CLK_PSADIV0_bm = (1<<2) ; Prescaler A Division Factor bit 0 mask
        .equ CLK_PSADIV0_bp = 2 ; Prescaler A Division Factor bit 0 position
        .equ CLK_PSADIV1_bm = (1<<3) ; Prescaler A Division Factor bit 1 mask
        .equ CLK_PSADIV1_bp = 3 ; Prescaler A Division Factor bit 1 position
        .equ CLK_PSADIV2_bm = (1<<4) ; Prescaler A Division Factor bit 2 mask
        .equ CLK_PSADIV2_bp = 4 ; Prescaler A Division Factor bit 2 position
        .equ CLK_PSADIV3_bm = (1<<5) ; Prescaler A Division Factor bit 3 mask
        .equ CLK_PSADIV3_bp = 5 ; Prescaler A Division Factor bit 3 position
        .equ CLK_PSADIV4_bm = (1<<6) ; Prescaler A Division Factor bit 4 mask
        .equ CLK_PSADIV4_bp = 6 ; Prescaler A Division Factor bit 4 position
        .equ CLK_PSBCDIV_gm = 0x03 ; Prescaler B and C Division factor group mask
        .equ CLK_PSBCDIV_gp = 0 ; Prescaler B and C Division factor group position
        .equ CLK_PSBCDIV0_bm = (1<<0) ; Prescaler B and C Division factor bit 0 mask
        .equ CLK_PSBCDIV0_bp = 0 ; Prescaler B and C Division factor bit 0 position
        .equ CLK_PSBCDIV1_bm = (1<<1) ; Prescaler B and C Division factor bit 1 mask
        .equ CLK_PSBCDIV1_bp = 1 ; Prescaler B and C Division factor bit 1 position
        
        ; CLK_LOCK masks
        .equ CLK_LOCK_bm = 0x01 ; Clock System Lock bit mask
        .equ CLK_LOCK_bp = 0 ; Clock System Lock bit position
        
        ; CLK_RTCCTRL masks
        .equ CLK_RTCSRC_gm = 0x0E ; Clock Source group mask
        .equ CLK_RTCSRC_gp = 1 ; Clock Source group position
        .equ CLK_RTCSRC0_bm = (1<<1) ; Clock Source bit 0 mask
        .equ CLK_RTCSRC0_bp = 1 ; Clock Source bit 0 position
        .equ CLK_RTCSRC1_bm = (1<<2) ; Clock Source bit 1 mask
        .equ CLK_RTCSRC1_bp = 2 ; Clock Source bit 1 position
        .equ CLK_RTCSRC2_bm = (1<<3) ; Clock Source bit 2 mask
        .equ CLK_RTCSRC2_bp = 3 ; Clock Source bit 2 position
        .equ CLK_RTCEN_bm = 0x01 ; Clock Source Enable bit mask
        .equ CLK_RTCEN_bp = 0 ; Clock Source Enable bit position
        
        ; PR_PRGEN masks
        .equ PR_XCL_bm = 0x80 ; XMEGA Custom Logic bit mask
        .equ PR_XCL_bp = 7 ; XMEGA Custom Logic bit position
        .equ PR_RTC_bm = 0x04 ; Real-time Counter bit mask
        .equ PR_RTC_bp = 2 ; Real-time Counter bit position
        .equ PR_EVSYS_bm = 0x02 ; Event System bit mask
        .equ PR_EVSYS_bp = 1 ; Event System bit position
        .equ PR_EDMA_bm = 0x01 ; Enhanced DMA-Controller bit mask
        .equ PR_EDMA_bp = 0 ; Enhanced DMA-Controller bit position
        
        ; PR_PRPA masks
        .equ PR_DAC_bm = 0x04 ; Port A DAC bit mask
        .equ PR_DAC_bp = 2 ; Port A DAC bit position
        .equ PR_ADC_bm = 0x02 ; Port A ADC bit mask
        .equ PR_ADC_bp = 1 ; Port A ADC bit position
        .equ PR_AC_bm = 0x01 ; Port A Analog Comparator bit mask
        .equ PR_AC_bp = 0 ; Port A Analog Comparator bit position
        
        ; PR_PRPC masks
        .equ PR_TWI_bm = 0x40 ; Port C Two-wire Interface bit mask
        .equ PR_TWI_bp = 6 ; Port C Two-wire Interface bit position
        .equ PR_USART0_bm = 0x10 ; Port C USART0 bit mask
        .equ PR_USART0_bp = 4 ; Port C USART0 bit position
        .equ PR_SPI_bm = 0x08 ; Port C SPI bit mask
        .equ PR_SPI_bp = 3 ; Port C SPI bit position
        .equ PR_HIRES_bm = 0x04 ; Port C WEX bit mask
        .equ PR_HIRES_bp = 2 ; Port C WEX bit position
        .equ PR_TC5_bm = 0x02 ; Port C Timer/Counter5 bit mask
        .equ PR_TC5_bp = 1 ; Port C Timer/Counter5 bit position
        .equ PR_TC4_bm = 0x01 ; Port C Timer/Counter4 bit mask
        .equ PR_TC4_bp = 0 ; Port C Timer/Counter4 bit position
        
        ; PR_PRPD masks
        ; Masks for PR_USART0 already defined
        ; Masks for PR_TC5 already defined
        
        ; System Clock Selection
        .equ CLK_SCLKSEL_RC2M_gc = (0x00<<0) ; Internal 2 MHz RC Oscillator
        .equ CLK_SCLKSEL_RC32M_gc = (0x01<<0) ; Internal 32 MHz RC Oscillator
        .equ CLK_SCLKSEL_RC32K_gc = (0x02<<0) ; Internal 32.768 kHz RC Oscillator
        .equ CLK_SCLKSEL_XOSC_gc = (0x03<<0) ; External Crystal Oscillator or Clock
        .equ CLK_SCLKSEL_PLL_gc = (0x04<<0) ; Phase Locked Loop
        .equ CLK_SCLKSEL_RC8M_gc = (0x05<<0) ; Internal 8 MHz RC Oscillator
        
        ; Prescaler A Division Factor
        .equ CLK_PSADIV_1_gc = (0x00<<2) ; Divide by 1
        .equ CLK_PSADIV_2_gc = (0x01<<2) ; Divide by 2
        .equ CLK_PSADIV_4_gc = (0x03<<2) ; Divide by 4
        .equ CLK_PSADIV_8_gc = (0x05<<2) ; Divide by 8
        .equ CLK_PSADIV_16_gc = (0x07<<2) ; Divide by 16
        .equ CLK_PSADIV_32_gc = (0x09<<2) ; Divide by 32
        .equ CLK_PSADIV_64_gc = (0x0B<<2) ; Divide by 64
        .equ CLK_PSADIV_128_gc = (0x0D<<2) ; Divide by 128
        .equ CLK_PSADIV_256_gc = (0x0F<<2) ; Divide by 256
        .equ CLK_PSADIV_512_gc = (0x11<<2) ; Divide by 512
        .equ CLK_PSADIV_6_gc = (0x13<<2) ; Divide by 6
        .equ CLK_PSADIV_10_gc = (0x15<<2) ; Divide by 10
        .equ CLK_PSADIV_12_gc = (0x17<<2) ; Divide by 12
        .equ CLK_PSADIV_24_gc = (0x19<<2) ; Divide by 24
        .equ CLK_PSADIV_48_gc = (0x1B<<2) ; Divide by 48
        
        ; Prescaler B and C Division Factor
        .equ CLK_PSBCDIV_1_1_gc = (0x00<<0) ; Divide B by 1 and C by 1
        .equ CLK_PSBCDIV_1_2_gc = (0x01<<0) ; Divide B by 1 and C by 2
        .equ CLK_PSBCDIV_4_1_gc = (0x02<<0) ; Divide B by 4 and C by 1
        .equ CLK_PSBCDIV_2_2_gc = (0x03<<0) ; Divide B by 2 and C by 2
        
        ; RTC Clock Source
        .equ CLK_RTCSRC_ULP_gc = (0x00<<1) ; 1.024 kHz from internal 32kHz ULP
        .equ CLK_RTCSRC_TOSC_gc = (0x01<<1) ; 1.024 kHz from 32.768 kHz crystal oscillator on TOSC
        .equ CLK_RTCSRC_RCOSC_gc = (0x02<<1) ; 1.024 kHz from internal 32.768 kHz RC oscillator
        .equ CLK_RTCSRC_TOSC32_gc = (0x05<<1) ; 32.768 kHz from 32.768 kHz crystal oscillator on TOSC
        .equ CLK_RTCSRC_RCOSC32_gc = (0x06<<1) ; 32.768 kHz from internal 32.768 kHz RC oscillator
        .equ CLK_RTCSRC_EXTCLK_gc = (0x07<<1) ; External Clock from TOSC1

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	CTRL	-	-	-	-	-	SCLKSEL[2:0]
0x0001	PSCTRL	-	PSADIV[4:0]					PSBCDIV[1:0]
0x0002	LOCK	-	-	-	-	-	-	-	LOCK
0x0003	RTCCTRL	-	-	-	-	RTCSRC[2:0]			RTCEN
0x0004	Reserved	-	-	-	-	-	-	-	-
0x0005	Reserved	-	-	-	-	-	-	-	-
0x0006	Reserved	-	-	-	-	-	-	-	-
0x0007	Reserved	-	-	-	-	-	-	-	-

0x0048 SLEEP Sleep Controller

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	CTRL	-	-	-	-	SMODE[2:0]			SEN

0x0050 OSC Ocilator Control Register

Aliases

        
        ;*************************************************************************
        ;** OSC - Oscillator
        ;*************************************************************************

        ; OSC_CTRL masks
        .equ OSC_RC8MLPM_bm = 0x40 ; Internal 8 MHz RC Low Power Mode Enable bit mask
        .equ OSC_RC8MLPM_bp = 6 ; Internal 8 MHz RC Low Power Mode Enable bit position
        .equ OSC_RC8MEN_bm = 0x20 ; Internal 8 MHz RC Oscillator Enable bit mask
        .equ OSC_RC8MEN_bp = 5 ; Internal 8 MHz RC Oscillator Enable bit position
        .equ OSC_PLLEN_bm = 0x10 ; PLL Enable bit mask
        .equ OSC_PLLEN_bp = 4 ; PLL Enable bit position
        .equ OSC_XOSCEN_bm = 0x08 ; External Oscillator Enable bit mask
        .equ OSC_XOSCEN_bp = 3 ; External Oscillator Enable bit position
        .equ OSC_RC32KEN_bm = 0x04 ; Internal 32.768 kHz RC Oscillator Enable bit mask
        .equ OSC_RC32KEN_bp = 2 ; Internal 32.768 kHz RC Oscillator Enable bit position
        .equ OSC_RC32MEN_bm = 0x02 ; Internal 32 MHz RC Oscillator Enable bit mask
        .equ OSC_RC32MEN_bp = 1 ; Internal 32 MHz RC Oscillator Enable bit position
        .equ OSC_RC2MEN_bm = 0x01 ; Internal 2 MHz RC Oscillator Enable bit mask
        .equ OSC_RC2MEN_bp = 0 ; Internal 2 MHz RC Oscillator Enable bit position

        ; OSC_STATUS masks
        .equ OSC_RC8MRDY_bm = 0x20 ; Internal 8 MHz RC Oscillator Ready bit mask
        .equ OSC_RC8MRDY_bp = 5 ; Internal 8 MHz RC Oscillator Ready bit position
        .equ OSC_PLLRDY_bm = 0x10 ; PLL Ready bit mask
        .equ OSC_PLLRDY_bp = 4 ; PLL Ready bit position
        .equ OSC_XOSCRDY_bm = 0x08 ; External Oscillator Ready bit mask
        .equ OSC_XOSCRDY_bp = 3 ; External Oscillator Ready bit position
        .equ OSC_RC32KRDY_bm = 0x04 ; Internal 32.768 kHz RC Oscillator Ready bit mask
        .equ OSC_RC32KRDY_bp = 2 ; Internal 32.768 kHz RC Oscillator Ready bit position
        .equ OSC_RC32MRDY_bm = 0x02 ; Internal 32 MHz RC Oscillator Ready bit mask
        .equ OSC_RC32MRDY_bp = 1 ; Internal 32 MHz RC Oscillator Ready bit position
        .equ OSC_RC2MRDY_bm = 0x01 ; Internal 2 MHz RC Oscillator Ready bit mask
        .equ OSC_RC2MRDY_bp = 0 ; Internal 2 MHz RC Oscillator Ready bit position

        ; OSC_XOSCCTRL masks
        .equ OSC_FRQRANGE_gm = 0xC0 ; Frequency Range group mask
        .equ OSC_FRQRANGE_gp = 6 ; Frequency Range group position
        .equ OSC_FRQRANGE0_bm = (1<<6) ; Frequency Range bit 0 mask
        .equ OSC_FRQRANGE0_bp = 6 ; Frequency Range bit 0 position
        .equ OSC_FRQRANGE1_bm = (1<<7) ; Frequency Range bit 1 mask
        .equ OSC_FRQRANGE1_bp = 7 ; Frequency Range bit 1 position
        .equ OSC_X32KLPM_bm = 0x20 ; 32.768 kHz XTAL OSC Low-power Mode bit mask
        .equ OSC_X32KLPM_bp = 5 ; 32.768 kHz XTAL OSC Low-power Mode bit position
        .equ OSC_XOSCPWR_bm = 0x10 ; 16 MHz Crystal Oscillator High Power mode bit mask
        .equ OSC_XOSCPWR_bp = 4 ; 16 MHz Crystal Oscillator High Power mode bit position
        .equ OSC_XOSCSEL_gm = 0x1F ; External Oscillator Selection and Startup Time group mask
        .equ OSC_XOSCSEL_gp = 0 ; External Oscillator Selection and Startup Time group position
        .equ OSC_XOSCSEL0_bm = (1<<0) ; External Oscillator Selection and Startup Time bit 0 mask
        .equ OSC_XOSCSEL0_bp = 0 ; External Oscillator Selection and Startup Time bit 0 position
        .equ OSC_XOSCSEL1_bm = (1<<1) ; External Oscillator Selection and Startup Time bit 1 mask
        .equ OSC_XOSCSEL1_bp = 1 ; External Oscillator Selection and Startup Time bit 1 position
        .equ OSC_XOSCSEL2_bm = (1<<2) ; External Oscillator Selection and Startup Time bit 2 mask
        .equ OSC_XOSCSEL2_bp = 2 ; External Oscillator Selection and Startup Time bit 2 position
        .equ OSC_XOSCSEL3_bm = (1<<3) ; External Oscillator Selection and Startup Time bit 3 mask
        .equ OSC_XOSCSEL3_bp = 3 ; External Oscillator Selection and Startup Time bit 3 position
        .equ OSC_XOSCSEL4_bm = (1<<4) ; External Oscillator Selection and Startup Time bit 4 mask
        .equ OSC_XOSCSEL4_bp = 4 ; External Oscillator Selection and Startup Time bit 4 position

        ; OSC_XOSCFAIL masks
        .equ OSC_PLLFDIF_bm = 0x08 ; PLL Failure Detection Interrupt Flag bit mask
        .equ OSC_PLLFDIF_bp = 3 ; PLL Failure Detection Interrupt Flag bit position
        .equ OSC_PLLFDEN_bm = 0x04 ; PLL Failure Detection Enable bit mask
        .equ OSC_PLLFDEN_bp = 2 ; PLL Failure Detection Enable bit position
        .equ OSC_XOSCFDIF_bm = 0x02 ; XOSC Failure Detection Interrupt Flag bit mask
        .equ OSC_XOSCFDIF_bp = 1 ; XOSC Failure Detection Interrupt Flag bit position
        .equ OSC_XOSCFDEN_bm = 0x01 ; XOSC Failure Detection Enable bit mask
        .equ OSC_XOSCFDEN_bp = 0 ; XOSC Failure Detection Enable bit position

        ; OSC_PLLCTRL masks
        .equ OSC_PLLSRC_gm = 0xC0 ; Clock Source group mask
        .equ OSC_PLLSRC_gp = 6 ; Clock Source group position
        .equ OSC_PLLSRC0_bm = (1<<6) ; Clock Source bit 0 mask
        .equ OSC_PLLSRC0_bp = 6 ; Clock Source bit 0 position
        .equ OSC_PLLSRC1_bm = (1<<7) ; Clock Source bit 1 mask
        .equ OSC_PLLSRC1_bp = 7 ; Clock Source bit 1 position
        .equ OSC_PLLDIV_bm = 0x20 ; Divide by 2 bit mask
        .equ OSC_PLLDIV_bp = 5 ; Divide by 2 bit position
        .equ OSC_PLLFAC_gm = 0x1F ; Multiplication Factor group mask
        .equ OSC_PLLFAC_gp = 0 ; Multiplication Factor group position
        .equ OSC_PLLFAC0_bm = (1<<0) ; Multiplication Factor bit 0 mask
        .equ OSC_PLLFAC0_bp = 0 ; Multiplication Factor bit 0 position
        .equ OSC_PLLFAC1_bm = (1<<1) ; Multiplication Factor bit 1 mask
        .equ OSC_PLLFAC1_bp = 1 ; Multiplication Factor bit 1 position
        .equ OSC_PLLFAC2_bm = (1<<2) ; Multiplication Factor bit 2 mask
        .equ OSC_PLLFAC2_bp = 2 ; Multiplication Factor bit 2 position
        .equ OSC_PLLFAC3_bm = (1<<3) ; Multiplication Factor bit 3 mask
        .equ OSC_PLLFAC3_bp = 3 ; Multiplication Factor bit 3 position
        .equ OSC_PLLFAC4_bm = (1<<4) ; Multiplication Factor bit 4 mask
        .equ OSC_PLLFAC4_bp = 4 ; Multiplication Factor bit 4 position

        ; OSC_DFLLCTRL masks
        .equ OSC_RC32MCREF_gm = 0x06 ; 32 MHz DFLL Calibration Reference group mask
        .equ OSC_RC32MCREF_gp = 1 ; 32 MHz DFLL Calibration Reference group position
        .equ OSC_RC32MCREF0_bm = (1<<1) ; 32 MHz DFLL Calibration Reference bit 0 mask
        .equ OSC_RC32MCREF0_bp = 1 ; 32 MHz DFLL Calibration Reference bit 0 position
        .equ OSC_RC32MCREF1_bm = (1<<2) ; 32 MHz DFLL Calibration Reference bit 1 mask
        .equ OSC_RC32MCREF1_bp = 2 ; 32 MHz DFLL Calibration Reference bit 1 position

        ; OSC_RC8MCAL masks
        .equ OSC_RC8MCAL_gm = 0xFF ; Calibration Bits group mask
        .equ OSC_RC8MCAL_gp = 0 ; Calibration Bits group position
        .equ OSC_RC8MCAL0_bm = (1<<0) ; Calibration Bits bit 0 mask
        .equ OSC_RC8MCAL0_bp = 0 ; Calibration Bits bit 0 position
        .equ OSC_RC8MCAL1_bm = (1<<1) ; Calibration Bits bit 1 mask
        .equ OSC_RC8MCAL1_bp = 1 ; Calibration Bits bit 1 position
        .equ OSC_RC8MCAL2_bm = (1<<2) ; Calibration Bits bit 2 mask
        .equ OSC_RC8MCAL2_bp = 2 ; Calibration Bits bit 2 position
        .equ OSC_RC8MCAL3_bm = (1<<3) ; Calibration Bits bit 3 mask
        .equ OSC_RC8MCAL3_bp = 3 ; Calibration Bits bit 3 position
        .equ OSC_RC8MCAL4_bm = (1<<4) ; Calibration Bits bit 4 mask
        .equ OSC_RC8MCAL4_bp = 4 ; Calibration Bits bit 4 position
        .equ OSC_RC8MCAL5_bm = (1<<5) ; Calibration Bits bit 5 mask
        .equ OSC_RC8MCAL5_bp = 5 ; Calibration Bits bit 5 position
        .equ OSC_RC8MCAL6_bm = (1<<6) ; Calibration Bits bit 6 mask
        .equ OSC_RC8MCAL6_bp = 6 ; Calibration Bits bit 6 position
        .equ OSC_RC8MCAL7_bm = (1<<7) ; Calibration Bits bit 7 mask
        .equ OSC_RC8MCAL7_bp = 7 ; Calibration Bits bit 7 position

        ; Oscillator Frequency Range
        .equ OSC_FRQRANGE_04TO2_gc = (0x00<<6) ; 0.4 - 2 MHz
        .equ OSC_FRQRANGE_2TO9_gc = (0x01<<6) ; 2 - 9 MHz
        .equ OSC_FRQRANGE_9TO12_gc = (0x02<<6) ; 9 - 12 MHz
        .equ OSC_FRQRANGE_12TO16_gc = (0x03<<6) ; 12 - 16 MHz

        ; External Oscillator Selection and Startup Time
        .equ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0) ; External Clock on port R1 - 6 CLK
        .equ OSC_XOSCSEL_32KHz_gc = (0x02<<0) ; 32.768 kHz TOSC - 32K CLK
        .equ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0) ; 0.4-16 MHz XTAL - 256 CLK
        .equ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0) ; 0.4-16 MHz XTAL - 1K CLK
        .equ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0) ; 0.4-16 MHz XTAL - 16K CLK
        .equ OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0) ; External Clock on port C4 - 6 CLK

        ; PLL Clock Source
        .equ OSC_PLLSRC_RC2M_gc = (0x00<<6) ; Internal 2 MHz RC Oscillator
        .equ OSC_PLLSRC_RC8M_gc = (0x01<<6) ; Internal 8 MHz RC Oscillator
        .equ OSC_PLLSRC_RC32M_gc = (0x02<<6) ; Internal 32 MHz RC Oscillator
        .equ OSC_PLLSRC_XOSC_gc = (0x03<<6) ; External Oscillator

        ; 32 MHz DFLL Calibration Reference
        .equ OSC_RC32MCREF_RC32K_gc = (0x00<<1) ; Internal 32.768 kHz RC Oscillator
        .equ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1) ; External 32.768 kHz Crystal Oscillator

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	CTRL	-	RC8MLPM	RC8MEN	PLLEN	XOSCEN	RC32KEN	RC32MEN	RC2MEN
0x0001	STATUS	-	-	RC8MRDY	PLLRDY	XOSCRDY	RC32KRDY	RC32MRDY	RC2MRDY
0X0002	XOSCCTRL	FRQRANGE1	FRQRANGE0	X32KLPM	XOSCPWR	XOSCSEL[3:0]
0X0002	XOSCCTRL	FRQRANGE1	FRQRANGE0	X32KLPM	XOSCSEL[4]	XOSCSEL[3:0]
0x0003	XOSCFAIL	-	-	-	-	PLLFDIF	PLLFDEN	XOSCFDIF	XOSCFDEN
0X0004	RC32KCAL	RC32KCAL[7:0]
0x0005	PLLCTRL	PLLSCR[1:0]		PLLDIV	PLLFAC[4:0]
0x0006	DFLLCTRL	-	-	-	-	-	RC32MMCREF[1:0]		-
0x0007	RC8MCAL	RC8MCAL[7:0]

0x0060 DFLLRC32M DDFLL for the 32MHz Internal Oscillator

Aliases

        
        ;*************************************************************************
        ;** DFLL - DFLL
        ;*************************************************************************

        ; DFLL_CTRL masks
        .equ DFLL_ENABLE_bm = 0x01 ; DFLL Enable bit mask
        .equ DFLL_ENABLE_bp = 0 ; DFLL Enable bit position

        ; DFLL_CALA masks
        .equ DFLL_CALL_gm = 0x7F ; DFLL Calibration Value A group mask
        .equ DFLL_CALL_gp = 0 ; DFLL Calibration Value A group position
        .equ DFLL_CALL0_bm = (1<<0) ; DFLL Calibration Value A bit 0 mask
        .equ DFLL_CALL0_bp = 0 ; DFLL Calibration Value A bit 0 position
        .equ DFLL_CALL1_bm = (1<<1) ; DFLL Calibration Value A bit 1 mask
        .equ DFLL_CALL1_bp = 1 ; DFLL Calibration Value A bit 1 position
        .equ DFLL_CALL2_bm = (1<<2) ; DFLL Calibration Value A bit 2 mask
        .equ DFLL_CALL2_bp = 2 ; DFLL Calibration Value A bit 2 position
        .equ DFLL_CALL3_bm = (1<<3) ; DFLL Calibration Value A bit 3 mask
        .equ DFLL_CALL3_bp = 3 ; DFLL Calibration Value A bit 3 position
        .equ DFLL_CALL4_bm = (1<<4) ; DFLL Calibration Value A bit 4 mask
        .equ DFLL_CALL4_bp = 4 ; DFLL Calibration Value A bit 4 position
        .equ DFLL_CALL5_bm = (1<<5) ; DFLL Calibration Value A bit 5 mask
        .equ DFLL_CALL5_bp = 5 ; DFLL Calibration Value A bit 5 position
        .equ DFLL_CALL6_bm = (1<<6) ; DFLL Calibration Value A bit 6 mask
        .equ DFLL_CALL6_bp = 6 ; DFLL Calibration Value A bit 6 position

        ; DFLL_CALB masks
        .equ DFLL_CALH_gm = 0x3F ; DFLL Calibration Value B group mask
        .equ DFLL_CALH_gp = 0 ; DFLL Calibration Value B group position
        .equ DFLL_CALH0_bm = (1<<0) ; DFLL Calibration Value B bit 0 mask
        .equ DFLL_CALH0_bp = 0 ; DFLL Calibration Value B bit 0 position
        .equ DFLL_CALH1_bm = (1<<1) ; DFLL Calibration Value B bit 1 mask
        .equ DFLL_CALH1_bp = 1 ; DFLL Calibration Value B bit 1 position
        .equ DFLL_CALH2_bm = (1<<2) ; DFLL Calibration Value B bit 2 mask
        .equ DFLL_CALH2_bp = 2 ; DFLL Calibration Value B bit 2 position
        .equ DFLL_CALH3_bm = (1<<3) ; DFLL Calibration Value B bit 3 mask
        .equ DFLL_CALH3_bp = 3 ; DFLL Calibration Value B bit 3 position
        .equ DFLL_CALH4_bm = (1<<4) ; DFLL Calibration Value B bit 4 mask
        .equ DFLL_CALH4_bp = 4 ; DFLL Calibration Value B bit 4 position
        .equ DFLL_CALH5_bm = (1<<5) ; DFLL Calibration Value B bit 5 mask
        .equ DFLL_CALH5_bp = 5 ; DFLL Calibration Value B bit 5 position

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	CTRL	-	-	-	-	-	-	-	ENABLE
0x0001	Reserved	-	-	-	-	-	-	-	-
0x0002	CALA	-	CALA[6:0]
0x0003	CALB	-	-	CALB[5:0]
0X0004	Reserved	-	-	-	-	-	-	-	-
0x0005	COMP1	COMP[7:0]
0x0006	COMP2	COMP[15:8]
0x0007	Reserved	-	-	-	-	-	-	-	-

0x00B0 PORTCFG Port Configuration

Aliases

        
    ;*************************************************************************
    ;** PORTCFG - Port Configuration
    ;*************************************************************************
    
    .equ PORTCFG_MPCMASK = 176		// Multi-pin Configuration Mask
    .equ PORTCFG_CLKOUT = 180		// Clock Out Register
    .equ PORTCFG_ACEVOUT = 182		// Analog Comparator and Event Out Register
    .equ PORTCFG_SRLCTRL  = 183		// Slew Rate Limit Control Register
    ;*************************************************************************
    ;** PORTCFG - Port Configuration
    ;*************************************************************************
    .equ PORTCFG_MPCMASK_offset = 0x00		// Multi-pin Configuration Mask
    .equ PORTCFG_CLKOUT_offset = 0x04		// Clock Out Register
    .equ PORTCFG_ACEVOUT_offset = 0x06		// Analog Comparator and Event Out Register
    .equ PORTCFG_SRLCTRL_offset = 0x07		// Slew Rate Limit Control Register 
    ;*************************************************************************
    ;** PORTCFG - Port Configuration
    ;*************************************************************************

    ; PORTCFG_CLKOUT masks
    .equ PORTCFG_CLKEVPIN_bm = 0x80 ; Clock and Event Output Pin Select bit mask
    .equ PORTCFG_CLKEVPIN_bp = 7 ; Clock and Event Output Pin Select bit position
    .equ PORTCFG_RTCOUT_gm = 0x60 ; RTC Clock Output Enable group mask
    .equ PORTCFG_RTCOUT_gp = 5 ; RTC Clock Output Enable group position
    .equ PORTCFG_RTCOUT0_bm = (1<<5) ; RTC Clock Output Enable bit 0 mask
    .equ PORTCFG_RTCOUT0_bp = 5 ; RTC Clock Output Enable bit 0 position
    .equ PORTCFG_RTCOUT1_bm = (1<<6) ; RTC Clock Output Enable bit 1 mask
    .equ PORTCFG_RTCOUT1_bp = 6 ; RTC Clock Output Enable bit 1 position
    .equ PORTCFG_CLKOUTSEL_gm = 0x0C ; Clock Output Select group mask
    .equ PORTCFG_CLKOUTSEL_gp = 2 ; Clock Output Select group position
    .equ PORTCFG_CLKOUTSEL0_bm = (1<<2) ; Clock Output Select bit 0 mask
    .equ PORTCFG_CLKOUTSEL0_bp = 2 ; Clock Output Select bit 0 position
    .equ PORTCFG_CLKOUTSEL1_bm = (1<<3) ; Clock Output Select bit 1 mask
    .equ PORTCFG_CLKOUTSEL1_bp = 3 ; Clock Output Select bit 1 position
    .equ PORTCFG_CLKOUT_gm = 0x03 ; Clock Output Port group mask
    .equ PORTCFG_CLKOUT_gp = 0 ; Clock Output Port group position
    .equ PORTCFG_CLKOUT0_bm = (1<<0) ; Clock Output Port bit 0 mask
    .equ PORTCFG_CLKOUT0_bp = 0 ; Clock Output Port bit 0 position
    .equ PORTCFG_CLKOUT1_bm = (1<<1) ; Clock Output Port bit 1 mask
    .equ PORTCFG_CLKOUT1_bp = 1 ; Clock Output Port bit 1 position

    ; PORTCFG_ACEVOUT masks
    .equ PORTCFG_ACOUT_gm = 0xC0 ; Analog Comparator Output Port group mask
    .equ PORTCFG_ACOUT_gp = 6 ; Analog Comparator Output Port group position
    .equ PORTCFG_ACOUT0_bm = (1<<6) ; Analog Comparator Output Port bit 0 mask
    .equ PORTCFG_ACOUT0_bp = 6 ; Analog Comparator Output Port bit 0 position
    .equ PORTCFG_ACOUT1_bm = (1<<7) ; Analog Comparator Output Port bit 1 mask
    .equ PORTCFG_ACOUT1_bp = 7 ; Analog Comparator Output Port bit 1 position
    .equ PORTCFG_EVOUT_gm = 0x30 ; Event Channel Output Port group mask
    .equ PORTCFG_EVOUT_gp = 4 ; Event Channel Output Port group position
    .equ PORTCFG_EVOUT0_bm = (1<<4) ; Event Channel Output Port bit 0 mask
    .equ PORTCFG_EVOUT0_bp = 4 ; Event Channel Output Port bit 0 position
    .equ PORTCFG_EVOUT1_bm = (1<<5) ; Event Channel Output Port bit 1 mask
    .equ PORTCFG_EVOUT1_bp = 5 ; Event Channel Output Port bit 1 position
    .equ PORTCFG_EVASYEN_bm = 0x08 ; Asynchronous Event Enabled bit mask
    .equ PORTCFG_EVASYEN_bp = 3 ; Asynchronous Event Enabled bit position
    .equ PORTCFG_EVOUTSEL_gm = 0x07 ; Event Channel Output Selection group mask
    .equ PORTCFG_EVOUTSEL_gp = 0 ; Event Channel Output Selection group position
    .equ PORTCFG_EVOUTSEL0_bm = (1<<0) ; Event Channel Output Selection bit 0 mask
    .equ PORTCFG_EVOUTSEL0_bp = 0 ; Event Channel Output Selection bit 0 position
    .equ PORTCFG_EVOUTSEL1_bm = (1<<1) ; Event Channel Output Selection bit 1 mask
    .equ PORTCFG_EVOUTSEL1_bp = 1 ; Event Channel Output Selection bit 1 position
    .equ PORTCFG_EVOUTSEL2_bm = (1<<2) ; Event Channel Output Selection bit 2 mask
    .equ PORTCFG_EVOUTSEL2_bp = 2 ; Event Channel Output Selection bit 2 position

    ; PORTCFG_SRLCTRL  masks
    .equ PORTCFG_SRLENRA_bm = 0x01 ; Slew Rate Limit Enable on PORTA bit mask
    .equ PORTCFG_SRLENRA_bp = 0 ; Slew Rate Limit Enable on PORTA bit position
    .equ PORTCFG_SRLENRC_bm = 0x04 ; Slew Rate Limit Enable on PORTC bit mask
    .equ PORTCFG_SRLENRC_bp = 2 ; Slew Rate Limit Enable on PORTC bit position
    .equ PORTCFG_SRLENRD_bm = 0x08 ; Slew Rate Limit Enable on PORTD bit mask
    .equ PORTCFG_SRLENRD_bp = 3 ; Slew Rate Limit Enable on PORTD bit position
    .equ PORTCFG_SRLENRR_bm = 0x80 ; Slew Rate Limit Enable on PORTR bit mask
    .equ PORTCFG_SRLENRR_bp = 7 ; Slew Rate Limit Enable on PORTR bit position

    ; Clock and Event Output Port
    .equ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7) ; Clock and Event Ouput on PIN 7
    .equ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7) ; Clock and Event Ouput on PIN 4

    ; RTC Clock Output Port
    .equ PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5) ; System Clock Output Disabled
    .equ PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5) ; System Clock Output on Port C pin 6
    .equ PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5) ; System Clock Output on Port D pin 6
    .equ PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5) ; System Clock Output on Port R pin 0

    ; Peripheral Clock Output Select
    .equ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2) ; 1x Peripheral Clock Output to pin
    .equ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2) ; 2x Peripheral Clock Output to pin
    .equ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2) ; 4x Peripheral Clock Output to pin

    ; System Clock Output Port
    .equ PORTCFG_CLKOUT_OFF_gc = (0x00<<0) ; System Clock Output Disabled
    .equ PORTCFG_CLKOUT_PC7_gc = (0x01<<0) ; System Clock Output on Port C pin 7
    .equ PORTCFG_CLKOUT_PD7_gc = (0x02<<0) ; System Clock Output on Port D pin 7
    .equ PORTCFG_CLKOUT_PR0_gc = (0x03<<0) ; System Clock Output on Port R pin 0

    ; Analog Comparator Output Port
    .equ PORTCFG_ACOUT_PA_gc = (0x00<<6) ; Analog Comparator Outputs on Port A, Pin 6-7
    .equ PORTCFG_ACOUT_PC_gc = (0x01<<6) ; Analog Comparator Outputs on Port C, Pin 6-7
    .equ PORTCFG_ACOUT_PD_gc = (0x02<<6) ; Analog Comparator Outputs on Port D, Pin 6-7
    .equ PORTCFG_ACOUT_PR_gc = (0x03<<6) ; Analog Comparator Outputs on Port R, Pin 0-1

    ; Event Output Port
    .equ PORTCFG_EVOUT_OFF_gc = (0x00<<4) ; Event Output Disabled
    .equ PORTCFG_EVOUT_PC7_gc = (0x01<<4) ; Event Channel n Output on Port C pin 7
    .equ PORTCFG_EVOUT_PD7_gc = (0x02<<4) ; Event Channel n Output on Port D pin 7
    .equ PORTCFG_EVOUT_PR0_gc = (0x03<<4) ; Event Channel n Output on Port R pin 0

    ; Event Output Select
    .equ PORTCFG_EVOUTSEL_0_gc = (0x00<<0) ; Event Channel 0 output to pin
    .equ PORTCFG_EVOUTSEL_1_gc = (0x01<<0) ; Event Channel 1 output to pin
    .equ PORTCFG_EVOUTSEL_2_gc = (0x02<<0) ; Event Channel 2 output to pin
    .equ PORTCFG_EVOUTSEL_3_gc = (0x03<<0) ; Event Channel 3 output to pin
    .equ PORTCFG_EVOUTSEL_4_gc = (0x04<<0) ; Event Channel 4 output to pin
    .equ PORTCFG_EVOUTSEL_5_gc = (0x05<<0) ; Event Channel 5 output to pin
    .equ PORTCFG_EVOUTSEL_6_gc = (0x06<<0) ; Event Channel 6 output to pin
    .equ PORTCFG_EVOUTSEL_7_gc = (0x07<<0) ; Event Channel 7 output to pin

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	MPCMASK	MPMASK[7:0]
0x0001	Reserved	-	-	-	-	-	-	-	-
0x0002	Reserved	-	-	-	-	-	-	-	-
0x0003	Reserved	-	-	-	-	-	-	-	-
0x0004	CLKOUT	CLKEVPIN	RTCOUT[1:0]		-	CLKOUTSEL[1:0]		CLKOUT[1:0]
0x0005	Reserved	-	-	-	-	-	-	-	-
0x0006	ACEVOUT	ACOUT[1:0]		EVOUT[1:0]		EVASYEN	EVCTRL[2:0]
0x0007	SRLCTRL	SRLENR	-	-	-	SRLEND	SRLENC	-	SRLENA

0x0200 ADC/ADCA Analog to Digital + Converter on Port A

Aliases

    
    ;*************************************************************************
    ;** ADC - Analog/Digital Converter
    ;*************************************************************************
    .equ ADC_CH_CTRL_offset = 0x00		// Control Register
    .equ ADC_CH_MUXCTRL_offset = 0x01		// MUX Control
    .equ ADC_CH_INTCTRL_offset = 0x02		// Channel Interrupt Control Register
    .equ ADC_CH_INTFLAGS_offset = 0x03		// Interrupt Flags
    .equ ADC_CH_RES_offset = 0x04		// Channel Result
    .equ ADC_CH_SCAN_offset = 0x06		// Input Channel Scan
    .equ ADC_CH_CORRCTRL_offset = 0x07		// Correction Control Register
    .equ ADC_CH_OFFSETCORR0_offset = 0x08		// Offset Correction Register 0
    .equ ADC_CH_OFFSETCORR1_offset = 0x09		// Offset Correction Register 1
    .equ ADC_CH_GAINCORR0_offset = 0x0A		// Gain Correction Register 0
    .equ ADC_CH_GAINCORR1_offset = 0x0B		// Gain Correction Register 1
    .equ ADC_CH_AVGCTRL_offset = 0x0C		// Average Control Register
    .equ ADC_CTRLA_offset = 0x00		// Control Register A
    .equ ADC_CTRLB_offset = 0x01		// Control Register B
    .equ ADC_REFCTRL_offset = 0x02		// Reference Control
    .equ ADC_EVCTRL_offset = 0x03		// Event Control
    .equ ADC_PRESCALER_offset = 0x04		// Clock Prescaler
    .equ ADC_INTFLAGS_offset = 0x06		// Interrupt Flags
    .equ ADC_TEMP_offset = 0x07		// Temporary Register
    .equ ADC_SAMPCTRL_offset = 0x08		// ADC Sampling Time Control Register
    .equ ADC_CAL_offset = 0x0C		// Calibration Value
    .equ ADC_CH0RES_offset = 0x10		// Channel 0 Result
    .equ ADC_CMP_offset = 0x18		// Compare Value
    .equ ADC_CH0_offset = 0x20		// ADC Channel 0

    ;*************************************************************************
    ;** ADCA - Analog/Digital Converter
    ;*************************************************************************
    
    .equ ADCA_CTRLA = 512		// Control Register A
    .equ ADCA_CTRLB = 513		// Control Register B
    .equ ADCA_REFCTRL = 514		// Reference Control
    .equ ADCA_EVCTRL = 515		// Event Control
    .equ ADCA_PRESCALER = 516		// Clock Prescaler
    .equ ADCA_INTFLAGS = 518		// Interrupt Flags
    .equ ADCA_TEMP = 519		// Temporary Register
    .equ ADCA_SAMPCTRL = 520		// ADC Sampling Time Control Register
    .equ ADCA_CAL = 524		// Calibration Value
    .equ ADCA_CH0RES = 528		// Channel 0 Result
    .equ ADCA_CMP = 536		// Compare Value
    .equ ADCA_CH0_CTRL = 544		// Control Register
    .equ ADCA_CH0_MUXCTRL = 545		// MUX Control
    .equ ADCA_CH0_INTCTRL = 546		// Channel Interrupt Control Register
    .equ ADCA_CH0_INTFLAGS = 547		// Interrupt Flags
    .equ ADCA_CH0_RES = 548		// Channel Result
    .equ ADCA_CH0_SCAN = 550		// Input Channel Scan
    .equ ADCA_CH0_CORRCTRL = 551		// Correction Control Register
    .equ ADCA_CH0_OFFSETCORR0 = 552		// Offset Correction Register 0
    .equ ADCA_CH0_OFFSETCORR1 = 553		// Offset Correction Register 1
    .equ ADCA_CH0_GAINCORR0 = 554		// Gain Correction Register 0
    .equ ADCA_CH0_GAINCORR1 = 555		// Gain Correction Register 1
    .equ ADCA_CH0_AVGCTRL = 556		// Average Control Register

    ;*************************************************************************
    ;** ADC - Analog/Digital Converter
    ;*************************************************************************
    
    ; ADC_CH_CTRL masks
    .equ ADC_CH_START_bm = 0x80 ; Channel Start Conversion bit mask
    .equ ADC_CH_START_bp = 7 ; Channel Start Conversion bit position
    .equ ADC_CH_GAIN_gm = 0x1C ; Gain Factor group mask
    .equ ADC_CH_GAIN_gp = 2 ; Gain Factor group position
    .equ ADC_CH_GAIN0_bm = (1<<2) ; Gain Factor bit 0 mask
    .equ ADC_CH_GAIN0_bp = 2 ; Gain Factor bit 0 position
    .equ ADC_CH_GAIN1_bm = (1<<3) ; Gain Factor bit 1 mask
    .equ ADC_CH_GAIN1_bp = 3 ; Gain Factor bit 1 position
    .equ ADC_CH_GAIN2_bm = (1<<4) ; Gain Factor bit 2 mask
    .equ ADC_CH_GAIN2_bp = 4 ; Gain Factor bit 2 position
    .equ ADC_CH_INPUTMODE_gm = 0x03 ; Input Mode Select group mask
    .equ ADC_CH_INPUTMODE_gp = 0 ; Input Mode Select group position
    .equ ADC_CH_INPUTMODE0_bm = (1<<0) ; Input Mode Select bit 0 mask
    .equ ADC_CH_INPUTMODE0_bp = 0 ; Input Mode Select bit 0 position
    .equ ADC_CH_INPUTMODE1_bm = (1<<1) ; Input Mode Select bit 1 mask
    .equ ADC_CH_INPUTMODE1_bp = 1 ; Input Mode Select bit 1 position
    
    ; ADC_CH_MUXCTRL masks
    .equ ADC_CH_MUXPOS_gm = 0x78 ; MUX selection on Positive ADC Input group mask
    .equ ADC_CH_MUXPOS_gp = 3 ; MUX selection on Positive ADC Input group position
    .equ ADC_CH_MUXPOS0_bm = (1<<3) ; MUX selection on Positive ADC Input bit 0 mask
    .equ ADC_CH_MUXPOS0_bp = 3 ; MUX selection on Positive ADC Input bit 0 position
    .equ ADC_CH_MUXPOS1_bm = (1<<4) ; MUX selection on Positive ADC Input bit 1 mask
    .equ ADC_CH_MUXPOS1_bp = 4 ; MUX selection on Positive ADC Input bit 1 position
    .equ ADC_CH_MUXPOS2_bm = (1<<5) ; MUX selection on Positive ADC Input bit 2 mask
    .equ ADC_CH_MUXPOS2_bp = 5 ; MUX selection on Positive ADC Input bit 2 position
    .equ ADC_CH_MUXPOS3_bm = (1<<6) ; MUX selection on Positive ADC Input bit 3 mask
    .equ ADC_CH_MUXPOS3_bp = 6 ; MUX selection on Positive ADC Input bit 3 position
    .equ ADC_CH_MUXINT_gm = 0x78 ; MUX selection on Internal ADC Input group mask
    .equ ADC_CH_MUXINT_gp = 3 ; MUX selection on Internal ADC Input group position
    .equ ADC_CH_MUXINT0_bm = (1<<3) ; MUX selection on Internal ADC Input bit 0 mask
    .equ ADC_CH_MUXINT0_bp = 3 ; MUX selection on Internal ADC Input bit 0 position
    .equ ADC_CH_MUXINT1_bm = (1<<4) ; MUX selection on Internal ADC Input bit 1 mask
    .equ ADC_CH_MUXINT1_bp = 4 ; MUX selection on Internal ADC Input bit 1 position
    .equ ADC_CH_MUXINT2_bm = (1<<5) ; MUX selection on Internal ADC Input bit 2 mask
    .equ ADC_CH_MUXINT2_bp = 5 ; MUX selection on Internal ADC Input bit 2 position
    .equ ADC_CH_MUXINT3_bm = (1<<6) ; MUX selection on Internal ADC Input bit 3 mask
    .equ ADC_CH_MUXINT3_bp = 6 ; MUX selection on Internal ADC Input bit 3 position
    .equ ADC_CH_MUXNEG_gm = 0x03 ; MUX selection on Negative ADC Input group mask
    .equ ADC_CH_MUXNEG_gp = 0 ; MUX selection on Negative ADC Input group position
    .equ ADC_CH_MUXNEG0_bm = (1<<0) ; MUX selection on Negative ADC Input bit 0 mask
    .equ ADC_CH_MUXNEG0_bp = 0 ; MUX selection on Negative ADC Input bit 0 position
    .equ ADC_CH_MUXNEG1_bm = (1<<1) ; MUX selection on Negative ADC Input bit 1 mask
    .equ ADC_CH_MUXNEG1_bp = 1 ; MUX selection on Negative ADC Input bit 1 position
    .equ ADC_CH_MUXNEGL_gm = 0x03 ; MUX selection on Negative ADC Input Gain on 4 LSB pins group mask
    .equ ADC_CH_MUXNEGL_gp = 0 ; MUX selection on Negative ADC Input Gain on 4 LSB pins group position
    .equ ADC_CH_MUXNEGL0_bm = (1<<0) ; MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask
    .equ ADC_CH_MUXNEGL0_bp = 0 ; MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position
    .equ ADC_CH_MUXNEGL1_bm = (1<<1) ; MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask
    .equ ADC_CH_MUXNEGL1_bp = 1 ; MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position
    .equ ADC_CH_MUXNEGH_gm = 0x03 ; MUX selection on Negative ADC Input Gain on 4 MSB pins group mask
    .equ ADC_CH_MUXNEGH_gp = 0 ; MUX selection on Negative ADC Input Gain on 4 MSB pins group position
    .equ ADC_CH_MUXNEGH0_bm = (1<<0) ; MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask
    .equ ADC_CH_MUXNEGH0_bp = 0 ; MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position
    .equ ADC_CH_MUXNEGH1_bm = (1<<1) ; MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask
    .equ ADC_CH_MUXNEGH1_bp = 1 ; MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position
    
    ; ADC_CH_INTCTRL masks
    .equ ADC_CH_INTMODE_gm = 0x0C ; Interrupt Mode group mask
    .equ ADC_CH_INTMODE_gp = 2 ; Interrupt Mode group position
    .equ ADC_CH_INTMODE0_bm = (1<<2) ; Interrupt Mode bit 0 mask
    .equ ADC_CH_INTMODE0_bp = 2 ; Interrupt Mode bit 0 position
    .equ ADC_CH_INTMODE1_bm = (1<<3) ; Interrupt Mode bit 1 mask
    .equ ADC_CH_INTMODE1_bp = 3 ; Interrupt Mode bit 1 position
    .equ ADC_CH_INTLVL_gm = 0x03 ; Interrupt Level group mask
    .equ ADC_CH_INTLVL_gp = 0 ; Interrupt Level group position
    .equ ADC_CH_INTLVL0_bm = (1<<0) ; Interrupt Level bit 0 mask
    .equ ADC_CH_INTLVL0_bp = 0 ; Interrupt Level bit 0 position
    .equ ADC_CH_INTLVL1_bm = (1<<1) ; Interrupt Level bit 1 mask
    .equ ADC_CH_INTLVL1_bp = 1 ; Interrupt Level bit 1 position
    
    ; ADC_CH_INTFLAGS masks
    .equ ADC_CH_IF_bm = 0x01 ; Channel Interrupt Flag bit mask
    .equ ADC_CH_IF_bp = 0 ; Channel Interrupt Flag bit position
    
    ; ADC_CH_SCAN masks
    .equ ADC_CH_INPUTOFFSET_gm = 0xF0 ; Positive MUX Setting Offset group mask
    .equ ADC_CH_INPUTOFFSET_gp = 4 ; Positive MUX Setting Offset group position
    .equ ADC_CH_INPUTOFFSET0_bm = (1<<4) ; Positive MUX Setting Offset bit 0 mask
    .equ ADC_CH_INPUTOFFSET0_bp = 4 ; Positive MUX Setting Offset bit 0 position
    .equ ADC_CH_INPUTOFFSET1_bm = (1<<5) ; Positive MUX Setting Offset bit 1 mask
    .equ ADC_CH_INPUTOFFSET1_bp = 5 ; Positive MUX Setting Offset bit 1 position
    .equ ADC_CH_INPUTOFFSET2_bm = (1<<6) ; Positive MUX Setting Offset bit 2 mask
    .equ ADC_CH_INPUTOFFSET2_bp = 6 ; Positive MUX Setting Offset bit 2 position
    .equ ADC_CH_INPUTOFFSET3_bm = (1<<7) ; Positive MUX Setting Offset bit 3 mask
    .equ ADC_CH_INPUTOFFSET3_bp = 7 ; Positive MUX Setting Offset bit 3 position
    .equ ADC_CH_INPUTSCAN_gm = 0x0F ; Number of Channels Included in Scan group mask
    .equ ADC_CH_INPUTSCAN_gp = 0 ; Number of Channels Included in Scan group position
    .equ ADC_CH_INPUTSCAN0_bm = (1<<0) ; Number of Channels Included in Scan bit 0 mask
    .equ ADC_CH_INPUTSCAN0_bp = 0 ; Number of Channels Included in Scan bit 0 position
    .equ ADC_CH_INPUTSCAN1_bm = (1<<1) ; Number of Channels Included in Scan bit 1 mask
    .equ ADC_CH_INPUTSCAN1_bp = 1 ; Number of Channels Included in Scan bit 1 position
    .equ ADC_CH_INPUTSCAN2_bm = (1<<2) ; Number of Channels Included in Scan bit 2 mask
    .equ ADC_CH_INPUTSCAN2_bp = 2 ; Number of Channels Included in Scan bit 2 position
    .equ ADC_CH_INPUTSCAN3_bm = (1<<3) ; Number of Channels Included in Scan bit 3 mask
    .equ ADC_CH_INPUTSCAN3_bp = 3 ; Number of Channels Included in Scan bit 3 position
    
    ; ADC_CH_CORRCTRL masks
    .equ ADC_CH_CORREN_bm = 0x01 ; Correction Enable bit mask
    .equ ADC_CH_CORREN_bp = 0 ; Correction Enable bit position
    
    ; ADC_CH_OFFSETCORR1 masks
    .equ ADC_CH_OFFSETCORR_gm = 0x0F ; Offset Correction Byte 1 group mask
    .equ ADC_CH_OFFSETCORR_gp = 0 ; Offset Correction Byte 1 group position
    .equ ADC_CH_OFFSETCORR0_bm = (1<<0) ; Offset Correction Byte 1 bit 0 mask
    .equ ADC_CH_OFFSETCORR0_bp = 0 ; Offset Correction Byte 1 bit 0 position
    .equ ADC_CH_OFFSETCORR1_bm = (1<<1) ; Offset Correction Byte 1 bit 1 mask
    .equ ADC_CH_OFFSETCORR1_bp = 1 ; Offset Correction Byte 1 bit 1 position
    .equ ADC_CH_OFFSETCORR2_bm = (1<<2) ; Offset Correction Byte 1 bit 2 mask
    .equ ADC_CH_OFFSETCORR2_bp = 2 ; Offset Correction Byte 1 bit 2 position
    .equ ADC_CH_OFFSETCORR3_bm = (1<<3) ; Offset Correction Byte 1 bit 3 mask
    .equ ADC_CH_OFFSETCORR3_bp = 3 ; Offset Correction Byte 1 bit 3 position
    
    ; ADC_CH_GAINCORR1 masks
    .equ ADC_CH_GAINCORR_gm = 0x0F ; Gain Correction Byte 1 group mask
    .equ ADC_CH_GAINCORR_gp = 0 ; Gain Correction Byte 1 group position
    .equ ADC_CH_GAINCORR0_bm = (1<<0) ; Gain Correction Byte 1 bit 0 mask
    .equ ADC_CH_GAINCORR0_bp = 0 ; Gain Correction Byte 1 bit 0 position
    .equ ADC_CH_GAINCORR1_bm = (1<<1) ; Gain Correction Byte 1 bit 1 mask
    .equ ADC_CH_GAINCORR1_bp = 1 ; Gain Correction Byte 1 bit 1 position
    .equ ADC_CH_GAINCORR2_bm = (1<<2) ; Gain Correction Byte 1 bit 2 mask
    .equ ADC_CH_GAINCORR2_bp = 2 ; Gain Correction Byte 1 bit 2 position
    .equ ADC_CH_GAINCORR3_bm = (1<<3) ; Gain Correction Byte 1 bit 3 mask
    .equ ADC_CH_GAINCORR3_bp = 3 ; Gain Correction Byte 1 bit 3 position
    
    ; ADC_CH_AVGCTRL masks
    .equ ADC_CH_RIGHTSHIFT_gm = 0x70 ; Right Shift group mask
    .equ ADC_CH_RIGHTSHIFT_gp = 4 ; Right Shift group position
    .equ ADC_CH_RIGHTSHIFT0_bm = (1<<4) ; Right Shift bit 0 mask
    .equ ADC_CH_RIGHTSHIFT0_bp = 4 ; Right Shift bit 0 position
    .equ ADC_CH_RIGHTSHIFT1_bm = (1<<5) ; Right Shift bit 1 mask
    .equ ADC_CH_RIGHTSHIFT1_bp = 5 ; Right Shift bit 1 position
    .equ ADC_CH_RIGHTSHIFT2_bm = (1<<6) ; Right Shift bit 2 mask
    .equ ADC_CH_RIGHTSHIFT2_bp = 6 ; Right Shift bit 2 position
    .equ ADC_CH_SAMPNUM_gm = 0x0F ; Averaged Number of Samples group mask
    .equ ADC_CH_SAMPNUM_gp = 0 ; Averaged Number of Samples group position
    .equ ADC_CH_SAMPNUM0_bm = (1<<0) ; Averaged Number of Samples bit 0 mask
    .equ ADC_CH_SAMPNUM0_bp = 0 ; Averaged Number of Samples bit 0 position
    .equ ADC_CH_SAMPNUM1_bm = (1<<1) ; Averaged Number of Samples bit 1 mask
    .equ ADC_CH_SAMPNUM1_bp = 1 ; Averaged Number of Samples bit 1 position
    .equ ADC_CH_SAMPNUM2_bm = (1<<2) ; Averaged Number of Samples bit 2 mask
    .equ ADC_CH_SAMPNUM2_bp = 2 ; Averaged Number of Samples bit 2 position
    .equ ADC_CH_SAMPNUM3_bm = (1<<3) ; Averaged Number of Samples bit 3 mask
    .equ ADC_CH_SAMPNUM3_bp = 3 ; Averaged Number of Samples bit 3 position
    
    ; ADC_CTRLA masks
    .equ ADC_START_bm = 0x04 ; Start Conversion bit mask
    .equ ADC_START_bp = 2 ; Start Conversion bit position
    .equ ADC_FLUSH_bm = 0x02 ; ADC Flush bit mask
    .equ ADC_FLUSH_bp = 1 ; ADC Flush bit position
    .equ ADC_ENABLE_bm = 0x01 ; Enable ADC bit mask
    .equ ADC_ENABLE_bp = 0 ; Enable ADC bit position
    
    ; ADC_CTRLB masks
    .equ ADC_CURRLIMIT_gm = 0x60 ; Current Limitation group mask
    .equ ADC_CURRLIMIT_gp = 5 ; Current Limitation group position
    .equ ADC_CURRLIMIT0_bm = (1<<5) ; Current Limitation bit 0 mask
    .equ ADC_CURRLIMIT0_bp = 5 ; Current Limitation bit 0 position
    .equ ADC_CURRLIMIT1_bm = (1<<6) ; Current Limitation bit 1 mask
    .equ ADC_CURRLIMIT1_bp = 6 ; Current Limitation bit 1 position
    .equ ADC_CONMODE_bm = 0x10 ; Conversion Mode bit mask
    .equ ADC_CONMODE_bp = 4 ; Conversion Mode bit position
    .equ ADC_FREERUN_bm = 0x08 ; Free Running Mode Enable bit mask
    .equ ADC_FREERUN_bp = 3 ; Free Running Mode Enable bit position
    .equ ADC_RESOLUTION_gm = 0x06 ; Result Resolution group mask
    .equ ADC_RESOLUTION_gp = 1 ; Result Resolution group position
    .equ ADC_RESOLUTION0_bm = (1<<1) ; Result Resolution bit 0 mask
    .equ ADC_RESOLUTION0_bp = 1 ; Result Resolution bit 0 position
    .equ ADC_RESOLUTION1_bm = (1<<2) ; Result Resolution bit 1 mask
    .equ ADC_RESOLUTION1_bp = 2 ; Result Resolution bit 1 position
    
    ; ADC_REFCTRL masks
    .equ ADC_REFSEL_gm = 0x70 ; Reference Selection group mask
    .equ ADC_REFSEL_gp = 4 ; Reference Selection group position
    .equ ADC_REFSEL0_bm = (1<<4) ; Reference Selection bit 0 mask
    .equ ADC_REFSEL0_bp = 4 ; Reference Selection bit 0 position
    .equ ADC_REFSEL1_bm = (1<<5) ; Reference Selection bit 1 mask
    .equ ADC_REFSEL1_bp = 5 ; Reference Selection bit 1 position
    .equ ADC_REFSEL2_bm = (1<<6) ; Reference Selection bit 2 mask
    .equ ADC_REFSEL2_bp = 6 ; Reference Selection bit 2 position
    .equ ADC_BANDGAP_bm = 0x02 ; Bandgap enable bit mask
    .equ ADC_BANDGAP_bp = 1 ; Bandgap enable bit position
    .equ ADC_TEMPREF_bm = 0x01 ; Temperature Reference Enable bit mask
    .equ ADC_TEMPREF_bp = 0 ; Temperature Reference Enable bit position
    
    ; ADC_EVCTRL masks
    .equ ADC_EVSEL_gm = 0x38 ; Event Input Select group mask
    .equ ADC_EVSEL_gp = 3 ; Event Input Select group position
    .equ ADC_EVSEL0_bm = (1<<3) ; Event Input Select bit 0 mask
    .equ ADC_EVSEL0_bp = 3 ; Event Input Select bit 0 position
    .equ ADC_EVSEL1_bm = (1<<4) ; Event Input Select bit 1 mask
    .equ ADC_EVSEL1_bp = 4 ; Event Input Select bit 1 position
    .equ ADC_EVSEL2_bm = (1<<5) ; Event Input Select bit 2 mask
    .equ ADC_EVSEL2_bp = 5 ; Event Input Select bit 2 position
    .equ ADC_EVACT_gm = 0x07 ; Event Action Select group mask
    .equ ADC_EVACT_gp = 0 ; Event Action Select group position
    .equ ADC_EVACT0_bm = (1<<0) ; Event Action Select bit 0 mask
    .equ ADC_EVACT0_bp = 0 ; Event Action Select bit 0 position
    .equ ADC_EVACT1_bm = (1<<1) ; Event Action Select bit 1 mask
    .equ ADC_EVACT1_bp = 1 ; Event Action Select bit 1 position
    .equ ADC_EVACT2_bm = (1<<2) ; Event Action Select bit 2 mask
    .equ ADC_EVACT2_bp = 2 ; Event Action Select bit 2 position
    
    ; ADC_PRESCALER masks
    .equ ADC_PRESCALER_gm = 0x07 ; Clock Prescaler Selection group mask
    .equ ADC_PRESCALER_gp = 0 ; Clock Prescaler Selection group position
    .equ ADC_PRESCALER0_bm = (1<<0) ; Clock Prescaler Selection bit 0 mask
    .equ ADC_PRESCALER0_bp = 0 ; Clock Prescaler Selection bit 0 position
    .equ ADC_PRESCALER1_bm = (1<<1) ; Clock Prescaler Selection bit 1 mask
    .equ ADC_PRESCALER1_bp = 1 ; Clock Prescaler Selection bit 1 position
    .equ ADC_PRESCALER2_bm = (1<<2) ; Clock Prescaler Selection bit 2 mask
    .equ ADC_PRESCALER2_bp = 2 ; Clock Prescaler Selection bit 2 position
    
    ; ADC_INTFLAGS masks
    .equ ADC_CH0IF_bm = 0x01 ; Channel 0 Interrupt Flag bit mask
    .equ ADC_CH0IF_bp = 0 ; Channel 0 Interrupt Flag bit position
    
    ; ADC_SAMPCTRL masks
    .equ ADC_SAMPVAL_gm = 0x3F ; Sampling time control register group mask
    .equ ADC_SAMPVAL_gp = 0 ; Sampling time control register group position
    .equ ADC_SAMPVAL0_bm = (1<<0) ; Sampling time control register bit 0 mask
    .equ ADC_SAMPVAL0_bp = 0 ; Sampling time control register bit 0 position
    .equ ADC_SAMPVAL1_bm = (1<<1) ; Sampling time control register bit 1 mask
    .equ ADC_SAMPVAL1_bp = 1 ; Sampling time control register bit 1 position
    .equ ADC_SAMPVAL2_bm = (1<<2) ; Sampling time control register bit 2 mask
    .equ ADC_SAMPVAL2_bp = 2 ; Sampling time control register bit 2 position
    .equ ADC_SAMPVAL3_bm = (1<<3) ; Sampling time control register bit 3 mask
    .equ ADC_SAMPVAL3_bp = 3 ; Sampling time control register bit 3 position
    .equ ADC_SAMPVAL4_bm = (1<<4) ; Sampling time control register bit 4 mask
    .equ ADC_SAMPVAL4_bp = 4 ; Sampling time control register bit 4 position
    .equ ADC_SAMPVAL5_bm = (1<<5) ; Sampling time control register bit 5 mask
    .equ ADC_SAMPVAL5_bp = 5 ; Sampling time control register bit 5 position
    
    ; Current Limitation
    .equ ADC_CURRLIMIT_NO_gc = (0x00<<5) ; No current limit,     300ksps max sampling rate
    .equ ADC_CURRLIMIT_LOW_gc = (0x01<<5) ; Low current limit,    225ksps max sampling rate
    .equ ADC_CURRLIMIT_MED_gc = (0x02<<5) ; Medium current limit, 150ksps max sampling rate
    .equ ADC_CURRLIMIT_HIGH_gc = (0x03<<5) ; High current limit,   75ksps max sampling rate
    
    ; Conversion result resolution
    .equ ADC_RESOLUTION_12BIT_gc = (0x00<<1) ; 12-bit right-adjusted result
    .equ ADC_RESOLUTION_MT12BIT_gc = (0x01<<1) ; More than 12-bit (oversapling) right-adjusted result
    .equ ADC_RESOLUTION_8BIT_gc = (0x02<<1) ; 8-bit right-adjusted result
    .equ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1) ; 12-bit left-adjusted result
    
    ; Voltage reference selection
    .equ ADC_REFSEL_INT1V_gc = (0x00<<4) ; Internal 1V
    .equ ADC_REFSEL_INTVCC_gc = (0x01<<4) ; Internal VCC / 1.6
    .equ ADC_REFSEL_AREFA_gc = (0x02<<4) ; External reference on PORT A
    .equ ADC_REFSEL_AREFD_gc = (0x03<<4) ; External reference on PORT D
    .equ ADC_REFSEL_INTVCC2_gc = (0x04<<4) ; Internal VCC / 2
    
    ; Event channel input selection
    .equ ADC_EVSEL_0_gc = (0x00<<3) ; Event Channel 0
    .equ ADC_EVSEL_1_gc = (0x01<<3) ; Event Channel 1
    .equ ADC_EVSEL_2_gc = (0x02<<3) ; Event Channel 2
    .equ ADC_EVSEL_3_gc = (0x03<<3) ; Event Channel 3
    .equ ADC_EVSEL_4_gc = (0x04<<3) ; Event Channel 4
    .equ ADC_EVSEL_5_gc = (0x05<<3) ; Event Channel 5
    .equ ADC_EVSEL_6_gc = (0x06<<3) ; Event Channel 6
    .equ ADC_EVSEL_7_gc = (0x07<<3) ; Event Channel 7
    
    ; Event action selection
    .equ ADC_EVACT_NONE_gc = (0x00<<0) ; No event action
    .equ ADC_EVACT_CH0_gc = (0x01<<0) ; First event triggers channel conversion
    .equ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0) ; First event triggers synchronized sweep
    
    ; Clock prescaler
    .equ ADC_PRESCALER_DIV4_gc = (0x00<<0) ; Divide clock by 4
    .equ ADC_PRESCALER_DIV8_gc = (0x01<<0) ; Divide clock by 8
    .equ ADC_PRESCALER_DIV16_gc = (0x02<<0) ; Divide clock by 16
    .equ ADC_PRESCALER_DIV32_gc = (0x03<<0) ; Divide clock by 32
    .equ ADC_PRESCALER_DIV64_gc = (0x04<<0) ; Divide clock by 64
    .equ ADC_PRESCALER_DIV128_gc = (0x05<<0) ; Divide clock by 128
    .equ ADC_PRESCALER_DIV256_gc = (0x06<<0) ; Divide clock by 256
    .equ ADC_PRESCALER_DIV512_gc = (0x07<<0) ; Divide clock by 512
    
    ; Gain factor
    .equ ADC_CH_GAIN_1X_gc = (0x00<<2) ; 1x gain
    .equ ADC_CH_GAIN_2X_gc = (0x01<<2) ; 2x gain
    .equ ADC_CH_GAIN_4X_gc = (0x02<<2) ; 4x gain
    .equ ADC_CH_GAIN_8X_gc = (0x03<<2) ; 8x gain
    .equ ADC_CH_GAIN_16X_gc = (0x04<<2) ; 16x gain
    .equ ADC_CH_GAIN_32X_gc = (0x05<<2) ; 32x gain
    .equ ADC_CH_GAIN_64X_gc = (0x06<<2) ; 64x gain
    .equ ADC_CH_GAIN_DIV2_gc = (0x07<<2) ; x/2 gain
    
    ; Input mode
    .equ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0) ; Internal inputs, no gain
    .equ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0) ; Single-ended input, no gain
    .equ ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0) ; Differential input, gain with 4 LSB pins selection
    .equ ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0) ; Differential input, gain with 4 MSB pins selection
    
    ; Positive input multiplexer selection
    .equ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3) ; Input pin 0
    .equ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3) ; Input pin 1
    .equ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3) ; Input pin 2
    .equ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3) ; Input pin 3
    .equ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3) ; Input pin 4
    .equ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3) ; Input pin 5
    .equ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3) ; Input pin 6
    .equ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3) ; Input pin 7
    .equ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3) ; Input pin 8
    .equ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3) ; Input pin 9
    .equ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3) ; Input pin 10
    .equ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3) ; Input pin 11
    .equ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3) ; Input pin 12
    .equ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3) ; Input pin 13
    .equ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3) ; Input pin 14
    .equ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3) ; Input pin 15
    
    ; Internal input multiplexer selections
    .equ ADC_CH_MUXINT_TEMP_gc = (0x00<<3) ; Temperature Reference
    .equ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3) ; Bandgap Reference
    .equ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3) ; 1/10 Scaled VCC
    .equ ADC_CH_MUXINT_DAC_gc = (0x03<<3) ; DAC Output
    
    ; Negative input multiplexer selection when gain on 4 LSB pins
    .equ ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0) ; Input pin 0
    .equ ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0) ; Input pin 1
    .equ ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0) ; Input pin 2
    .equ ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0) ; Input pin 3
    .equ ADC_CH_MUXNEGL_GND_gc = (0x05<<0) ; PAD ground
    .equ ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0) ; Internal ground
    
    ; Negative input multiplexer selection when gain on 4 MSB pins
    .equ ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0) ; Input pin 4
    .equ ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0) ; Input pin 5
    .equ ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0) ; Input pin 6
    .equ ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0) ; Input pin 7
    .equ ADC_CH_MUXNEGH_INTGND_gc = (0x04<<0) ; Internal ground
    .equ ADC_CH_MUXNEGH_GND_gc = (0x05<<0) ; PAD ground
    
    ; Negative input multiplexer selection
    .equ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0) ; Input pin 0
    
    ; Interupt mode
    .equ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2) ; Interrupt on conversion complete
    .equ ADC_CH_INTMODE_BELOW_gc = (0x01<<2) ; Interrupt on result below compare value
    .equ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2) ; Interrupt on result above compare value
    
    ; Interrupt level
    .equ ADC_CH_INTLVL_OFF_gc = (0x00<<0) ; Interrupt disabled
    .equ ADC_CH_INTLVL_LO_gc = (0x01<<0) ; Low level
    .equ ADC_CH_INTLVL_MED_gc = (0x02<<0) ; Medium level
    .equ ADC_CH_INTLVL_HI_gc = (0x03<<0) ; High level
    
    ; Averaged Number of Samples
    .equ ADC_SAMPNUM_1X_gc = (0x00<<0) ; 1 Sample
    .equ ADC_SAMPNUM_2X_gc = (0x01<<0) ; 2 Samples
    .equ ADC_SAMPNUM_4X_gc = (0x02<<0) ; 4 Samples
    .equ ADC_SAMPNUM_8X_gc = (0x03<<0) ; 8 Samples
    .equ ADC_SAMPNUM_16X_gc = (0x04<<0) ; 16 Samples
    .equ ADC_SAMPNUM_32X_gc = (0x05<<0) ; 32 Samples
    .equ ADC_SAMPNUM_64X_gc = (0x06<<0) ; 64 Samples
    .equ ADC_SAMPNUM_128X_gc = (0x07<<0) ; 128 Samples
    .equ ADC_SAMPNUM_256X_gc = (0x08<<0) ; 256 Samples
    .equ ADC_SAMPNUM_512X_gc = (0x09<<0) ; 512 Samples
    .equ ADC_SAMPNUM_1024X_gc = (0x0A<<0) ; 1024 Samples

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0001	CTRLA	-	-	-	-	START	FLUCH	ENABLE
0x0001	CTRLB	-	CURRLIMIT[1:0]		CONVMODE	FREERUN	RESOLUTION[1:0]		-
0x0002	REFCTRL	-	REFSEL[2:0]			-	-	BANDGAP	TEMPREF
0x0003	EVCTRL	-	-	EVSEL[2:0]			EVACT[2:0]
0x0004	PRESCALER	-	-	-	-	-	PRESCALER[2:0]
0x0005	Reserved	-	-	-	-	-	-	-	-
0x0006	INTFLAGS	-	-	-	-	-	-	-	CH0IF
0x0007	TEMP	TEMP[7:0]
0x0008	SAMPCTRL	-	-	SAMPVAL[5:0]
0x0009	Reserved	-	-	-	-	-	-	-	-
0x000A	Reserved	-	-	-	-	-	-	-	-
0x000B	Reserved	-	-	-	-	-	-	-	-
0x000C	CALL	CAL[7:0]
0x000D	Reserved	-	-	-	-	-	-	-	-
0x000E	Reserved	-	-	-	-	-	-	-	-
0x000F	Reserved	-	-	-	-	-	-	-	-
0x00010	CH0RESL	CH0RES[7:0]
0x00011	CH0RESH	CH0RES[15:8]
0x0012	Reserved	-	-	-	-	-	-	-	-
0x0013	Reserved	-	-	-	-	-	-	-	-
0x0014	Reserved	-	-	-	-	-	-	-	-
0x0015	Reserved	-	-	-	-	-	-	-	-
0x0016	Reserved	-	-	-	-	-	-	-	-
0x0017	Reserved	-	-	-	-	-	-	-	-
0x00018	CMPL	CMPL[7:0]
0x00019	CMPH	CMPL[15:8]
0x001A	Reserved	-	-	-	-	-	-	-	-
0x001B	Reserved	-	-	-	-	-	-	-	-
0x001C	Reserved	-	-	-	-	-	-	-	-
0x001D	Reserved	-	-	-	-	-	-	-	-
0x001E	Reserved	-	-	-	-	-	-	-	-
0x001F	Reserved	-	-	-	-	-	-	-	-
Offset/Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0020/0x0000	CTRL	START	-	-	GAIN[2:]			INPUTMODE[1:0]
0x0021/0x0001	MUXCTRL	-	MUXPOS[3:0]				MUXNEG[2:0]
0x0022/0x0002	INTCTRL	-	-	-	-	INTMODE[1:0]		INTLVL[1:0]
0x0023/0x0003	INTFLAGS	-	-	-	-	-	-	-	IF
0x0024/0x0004	RESL	RESL[7:0]
0X0025/0x0005	RESH	RESL[15:8]
0x0026/0x0006	SCAN	INPUTOFSET[3:0]				INPUTSCAN[3:0]
0x0027/0x0007	CORRCTRL	-	-	-	-	-	-	-	CORREN
0x0028/0x0008	OFFSETCORR0	OFFSETCORR[7:0]
0x0029/0x0009	OFFSETCORR1	-	-	-	-	OFFSETCORR[11:8]
0x002A/0x000A	GAINCORR0	GAINCORR[7:0]
0x002B/0x000B	GAINCORR1	-	-	-	-	GAINCORR[11:8]
0x002C/0x000C	AVGCTRL	-	RIGHTSHIFT[2:0]			SAMPNUM[3:0]
0x002D/0x000D	Reserved	-	-	-	-	-	-	-	-
0x002E/0x000E	Reserved	-	-	-	-	-	-	-	-
0x002F/0x000F	Reserved	-	-	-	-	-	-	-	-
Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0030	Reserved	-	-	-	-	-	-	-	-
0x0038	Reserved	-	-	-	-	-	-	-	-

Aliases

            
        ;*************************************************************************
        ;** PORT - Port Configuration
        ;*************************************************************************
        .equ PORT_DIR_offset = 0x00		// I/O Port Data Direction
        .equ PORT_DIRSET_offset = 0x01		// I/O Port Data Direction Set
        .equ PORT_DIRCLR_offset = 0x02		// I/O Port Data Direction Clear
        .equ PORT_DIRTGL_offset = 0x03		// I/O Port Data Direction Toggle
        .equ PORT_OUT_offset = 0x04		// I/O Port Output
        .equ PORT_OUTSET_offset = 0x05		// I/O Port Output Set
        .equ PORT_OUTCLR_offset = 0x06		// I/O Port Output Clear
        .equ PORT_OUTTGL_offset = 0x07		// I/O Port Output Toggle
        .equ PORT_IN_offset = 0x08		// I/O port Input
        .equ PORT_INTCTRL_offset = 0x09		// Interrupt Control Register
        .equ PORT_INTMASK_offset = 0x0A		// Port Interrupt Mask
        .equ PORT_INTFLAGS_offset = 0x0C		// Interrupt Flag Register
        .equ PORT_REMAP_offset = 0x0E		// Pin Remap Register
        .equ PORT_PIN0CTRL_offset = 0x10		// Pin 0 Control Register
        .equ PORT_PIN1CTRL_offset = 0x11		// Pin 1 Control Register
        .equ PORT_PIN2CTRL_offset = 0x12		// Pin 2 Control Register
        .equ PORT_PIN3CTRL_offset = 0x13		// Pin 3 Control Register
        .equ PORT_PIN4CTRL_offset = 0x14		// Pin 4 Control Register
        .equ PORT_PIN5CTRL_offset = 0x15		// Pin 5 Control Register
        .equ PORT_PIN6CTRL_offset = 0x16		// Pin 6 Control Register
        .equ PORT_PIN7CTRL_offset = 0x17		// Pin 7 Control Register
        ;*************************************************************************
        ;** PORT - Port Configuration
        ;*************************************************************************

        ; PORT_INTCTRL masks
        .equ PORT_INTLVL_gm = 0x03 ; Port Interrupt Level group mask
        .equ PORT_INTLVL_gp = 0 ; Port Interrupt Level group position
        .equ PORT_INTLVL0_bm = (1<<0) ; Port Interrupt Level bit 0 mask
        .equ PORT_INTLVL0_bp = 0 ; Port Interrupt Level bit 0 position
        .equ PORT_INTLVL1_bm = (1<<1) ; Port Interrupt Level bit 1 mask
        .equ PORT_INTLVL1_bp = 1 ; Port Interrupt Level bit 1 position

        ; PORT_INTFLAGS masks
        .equ PORT_INT7IF_bm = 0x80 ; Pin 7 Interrupt Flag bit mask
        .equ PORT_INT7IF_bp = 7 ; Pin 7 Interrupt Flag bit position
        .equ PORT_INT6IF_bm = 0x40 ; Pin 6 Interrupt Flag bit mask
        .equ PORT_INT6IF_bp = 6 ; Pin 6 Interrupt Flag bit position
        .equ PORT_INT5IF_bm = 0x20 ; Pin 5 Interrupt Flag bit mask
        .equ PORT_INT5IF_bp = 5 ; Pin 5 Interrupt Flag bit position
        .equ PORT_INT4IF_bm = 0x10 ; Pin 4 Interrupt Flag bit mask
        .equ PORT_INT4IF_bp = 4 ; Pin 4 Interrupt Flag bit position
        .equ PORT_INT3IF_bm = 0x08 ; Pin 3 Interrupt Flag bit mask
        .equ PORT_INT3IF_bp = 3 ; Pin 3 Interrupt Flag bit position
        .equ PORT_INT2IF_bm = 0x04 ; Pin 2 Interrupt Flag bit mask
        .equ PORT_INT2IF_bp = 2 ; Pin 2 Interrupt Flag bit position
        .equ PORT_INT1IF_bm = 0x02 ; Pin 1 Interrupt Flag bit mask
        .equ PORT_INT1IF_bp = 1 ; Pin 1 Interrupt Flag bit position
        .equ PORT_INT0IF_bm = 0x01 ; Pin 0 Interrupt Flag bit mask
        .equ PORT_INT0IF_bp = 0 ; Pin 0 Interrupt Flag bit position

        ; PORT_REMAP masks
        .equ PORT_USART0_bm = 0x10 ; Usart0 bit mask
        .equ PORT_USART0_bp = 4 ; Usart0 bit position
        .equ PORT_TC4D_bm = 0x08 ; Timer/Counter 4 Output Compare D bit mask
        .equ PORT_TC4D_bp = 3 ; Timer/Counter 4 Output Compare D bit position
        .equ PORT_TC4C_bm = 0x04 ; Timer/Counter 4 Output Compare C bit mask
        .equ PORT_TC4C_bp = 2 ; Timer/Counter 4 Output Compare C bit position
        .equ PORT_TC4B_bm = 0x02 ; Timer/Counter 4 Output Compare B bit mask
        .equ PORT_TC4B_bp = 1 ; Timer/Counter 4 Output Compare B bit position
        .equ PORT_TC4A_bm = 0x01 ; Timer/Counter 4 Output Compare A bit mask
        .equ PORT_TC4A_bp = 0 ; Timer/Counter 4 Output Compare A bit position

        ; PORT_PIN0CTRL masks
        .equ PORT_INVEN_bm = 0x40 ; Inverted I/O Enable bit mask
        .equ PORT_INVEN_bp = 6 ; Inverted I/O Enable bit position
        .equ PORT_OPC_gm = 0x38 ; Output/Pull Configuration group mask
        .equ PORT_OPC_gp = 3 ; Output/Pull Configuration group position
        .equ PORT_OPC0_bm = (1<<3) ; Output/Pull Configuration bit 0 mask
        .equ PORT_OPC0_bp = 3 ; Output/Pull Configuration bit 0 position
        .equ PORT_OPC1_bm = (1<<4) ; Output/Pull Configuration bit 1 mask
        .equ PORT_OPC1_bp = 4 ; Output/Pull Configuration bit 1 position
        .equ PORT_OPC2_bm = (1<<5) ; Output/Pull Configuration bit 2 mask
        .equ PORT_OPC2_bp = 5 ; Output/Pull Configuration bit 2 position
        .equ PORT_ISC_gm = 0x07 ; Input/Sense Configuration group mask
        .equ PORT_ISC_gp = 0 ; Input/Sense Configuration group position
        .equ PORT_ISC0_bm = (1<<0) ; Input/Sense Configuration bit 0 mask
        .equ PORT_ISC0_bp = 0 ; Input/Sense Configuration bit 0 position
        .equ PORT_ISC1_bm = (1<<1) ; Input/Sense Configuration bit 1 mask
        .equ PORT_ISC1_bp = 1 ; Input/Sense Configuration bit 1 position
        .equ PORT_ISC2_bm = (1<<2) ; Input/Sense Configuration bit 2 mask
        .equ PORT_ISC2_bp = 2 ; Input/Sense Configuration bit 2 position

        ; PORT_PIN1CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN2CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN3CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN4CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN5CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN6CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN7CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; Port Interrupt Level
        .equ PORT_INTLVL_OFF_gc = (0x00<<0) ; Interrupt Disabled
        .equ PORT_INTLVL_LO_gc = (0x01<<0) ; Low Level
        .equ PORT_INTLVL_MED_gc = (0x02<<0) ; Medium Level
        .equ PORT_INTLVL_HI_gc = (0x03<<0) ; High Level

        ; Output/Pull Configuration
        .equ PORT_OPC_TOTEM_gc = (0x00<<3) ; Totempole
        .equ PORT_OPC_BUSKEEPER_gc = (0x01<<3) ; Totempole w/ Bus keeper on Input and Output
        .equ PORT_OPC_PULLDOWN_gc = (0x02<<3) ; Totempole w/ Pull-down on Input
        .equ PORT_OPC_PULLUP_gc = (0x03<<3) ; Totempole w/ Pull-up on Input
        .equ PORT_OPC_WIREDOR_gc = (0x04<<3) ; Wired OR
        .equ PORT_OPC_WIREDAND_gc = (0x05<<3) ; Wired AND
        .equ PORT_OPC_WIREDORPULL_gc = (0x06<<3) ; Wired OR w/ Pull-down
        .equ PORT_OPC_WIREDANDPULL_gc = (0x07<<3) ; Wired AND w/ Pull-up

        ; Input/Sense Configuration
        .equ PORT_ISC_BOTHEDGES_gc = (0x00<<0) ; Sense Both Edges
        .equ PORT_ISC_RISING_gc = (0x01<<0) ; Sense Rising Edge
        .equ PORT_ISC_FALLING_gc = (0x02<<0) ; Sense Falling Edge
        .equ PORT_ISC_LEVEL_gc = (0x03<<0) ; Sense Level (Transparent For Events)
        .equ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0) ; Digital Input Buffer Forced Enable
        .equ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0) ; Disable Digital Input Buffer

0x0600 PORTA Port A

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	DIR	DIR[7:0]
0x0001	DIRSET	DIRSET[7:0]
0x0002	DIRCLR	DIRCLR[7:0]
0x0003	DIRTGL	DIRTGL[7:0]
0x0004	OUT	OUT[7:0]
0x0005	OUTSET	OUTSET[7:0]
0x0006	OUTCLR	OUTCLR[7:0]
0x0007	OUTTGL	OUTTGL[7:0]
0x0008	IN	IN[7:0]
0x0009	INTCTRL	-	-	-	-	-	-	INTLVL[1:0]
0x000A	INTMASK	INTMASK[7:0]
0x000B	Reserved	-	-	-	-	-	-	-	-
0x000C	INTFLAGS	INT7IF	INT6IF	INT5IF	INT4IF	INT3IF	INT2IF	INT1IF	INT0IF
0x000D	Reserved	-	-	-	-	-	-	-	-
0x000E	REMAP	-	-	-	USART0	TC4D	TC4C	TC4B	TC4A
0x0010	PIN0CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0011	PIN1CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0012	PIN2CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0013	PIN3CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0014	PIN4CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0015	PIN5CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0016	PIN6CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0017	PIN7CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0018	Reserved	-	-	-	-	-	-	-	-
0x0019	Reserved	-	-	-	-	-	-	-	-
0x0019	Reserved	-	-	-	-	-	-	-	-
0x001A	Reserved	-	-	-	-	-	-	-	-
0x001B	Reserved	-	-	-	-	-	-	-	-
0x001C	Reserved	-	-	-	-	-	-	-	-
0x001D	Reserved	-	-	-	-	-	-	-	-
0x001E	Reserved	-	-	-	-	-	-	-	-
0x001F	Reserved	-	-	-	-	-	-	-	-

Aliases

            
        ;*************************************************************************
        ;** PORTC - Port Configuration
        ;*************************************************************************
        .equ PORTC_DIR = 1600		// I/O Port Data Direction
        .equ PORTC_DIRSET = 1601		// I/O Port Data Direction Set
        .equ PORTC_DIRCLR = 1602		// I/O Port Data Direction Clear
        .equ PORTC_DIRTGL = 1603		// I/O Port Data Direction Toggle
        .equ PORTC_OUT = 1604		// I/O Port Output
        .equ PORTC_OUTSET = 1605		// I/O Port Output Set
        .equ PORTC_OUTCLR = 1606		// I/O Port Output Clear
        .equ PORTC_OUTTGL = 1607		// I/O Port Output Toggle
        .equ PORTC_IN = 1608		// I/O port Input
        .equ PORTC_INTCTRL = 1609		// Interrupt Control Register
        .equ PORTC_INTMASK = 1610		// Port Interrupt Mask
        .equ PORTC_INTFLAGS = 1612		// Interrupt Flag Register
        .equ PORTC_REMAP = 1614		// Pin Remap Register
        .equ PORTC_PIN0CTRL = 1616		// Pin 0 Control Register
        .equ PORTC_PIN1CTRL = 1617		// Pin 1 Control Register
        .equ PORTC_PIN2CTRL = 1618		// Pin 2 Control Register
        .equ PORTC_PIN3CTRL = 1619		// Pin 3 Control Register
        .equ PORTC_PIN4CTRL = 1620		// Pin 4 Control Register
        .equ PORTC_PIN5CTRL = 1621		// Pin 5 Control Register
        .equ PORTC_PIN6CTRL = 1622		// Pin 6 Control Register
        .equ PORTC_PIN7CTRL = 1623		// Pin 7 Control Register
        ;*************************************************************************
        ;** PORT - Port Configuration
        ;*************************************************************************
        .equ PORT_DIR_offset = 0x00		// I/O Port Data Direction
        .equ PORT_DIRSET_offset = 0x01		// I/O Port Data Direction Set
        .equ PORT_DIRCLR_offset = 0x02		// I/O Port Data Direction Clear
        .equ PORT_DIRTGL_offset = 0x03		// I/O Port Data Direction Toggle
        .equ PORT_OUT_offset = 0x04		// I/O Port Output
        .equ PORT_OUTSET_offset = 0x05		// I/O Port Output Set
        .equ PORT_OUTCLR_offset = 0x06		// I/O Port Output Clear
        .equ PORT_OUTTGL_offset = 0x07		// I/O Port Output Toggle
        .equ PORT_IN_offset = 0x08		// I/O port Input
        .equ PORT_INTCTRL_offset = 0x09		// Interrupt Control Register
        .equ PORT_INTMASK_offset = 0x0A		// Port Interrupt Mask
        .equ PORT_INTFLAGS_offset = 0x0C		// Interrupt Flag Register
        .equ PORT_REMAP_offset = 0x0E		// Pin Remap Register
        .equ PORT_PIN0CTRL_offset = 0x10		// Pin 0 Control Register
        .equ PORT_PIN1CTRL_offset = 0x11		// Pin 1 Control Register
        .equ PORT_PIN2CTRL_offset = 0x12		// Pin 2 Control Register
        .equ PORT_PIN3CTRL_offset = 0x13		// Pin 3 Control Register
        .equ PORT_PIN4CTRL_offset = 0x14		// Pin 4 Control Register
        .equ PORT_PIN5CTRL_offset = 0x15		// Pin 5 Control Register
        .equ PORT_PIN6CTRL_offset = 0x16		// Pin 6 Control Register
        .equ PORT_PIN7CTRL_offset = 0x17		// Pin 7 Control Register
        ;*************************************************************************
        ;** PORT - Port Configuration
        ;*************************************************************************

        ; PORT_INTCTRL masks
        .equ PORT_INTLVL_gm = 0x03 ; Port Interrupt Level group mask
        .equ PORT_INTLVL_gp = 0 ; Port Interrupt Level group position
        .equ PORT_INTLVL0_bm = (1<<0) ; Port Interrupt Level bit 0 mask
        .equ PORT_INTLVL0_bp = 0 ; Port Interrupt Level bit 0 position
        .equ PORT_INTLVL1_bm = (1<<1) ; Port Interrupt Level bit 1 mask
        .equ PORT_INTLVL1_bp = 1 ; Port Interrupt Level bit 1 position

        ; PORT_INTFLAGS masks
        .equ PORT_INT7IF_bm = 0x80 ; Pin 7 Interrupt Flag bit mask
        .equ PORT_INT7IF_bp = 7 ; Pin 7 Interrupt Flag bit position
        .equ PORT_INT6IF_bm = 0x40 ; Pin 6 Interrupt Flag bit mask
        .equ PORT_INT6IF_bp = 6 ; Pin 6 Interrupt Flag bit position
        .equ PORT_INT5IF_bm = 0x20 ; Pin 5 Interrupt Flag bit mask
        .equ PORT_INT5IF_bp = 5 ; Pin 5 Interrupt Flag bit position
        .equ PORT_INT4IF_bm = 0x10 ; Pin 4 Interrupt Flag bit mask
        .equ PORT_INT4IF_bp = 4 ; Pin 4 Interrupt Flag bit position
        .equ PORT_INT3IF_bm = 0x08 ; Pin 3 Interrupt Flag bit mask
        .equ PORT_INT3IF_bp = 3 ; Pin 3 Interrupt Flag bit position
        .equ PORT_INT2IF_bm = 0x04 ; Pin 2 Interrupt Flag bit mask
        .equ PORT_INT2IF_bp = 2 ; Pin 2 Interrupt Flag bit position
        .equ PORT_INT1IF_bm = 0x02 ; Pin 1 Interrupt Flag bit mask
        .equ PORT_INT1IF_bp = 1 ; Pin 1 Interrupt Flag bit position
        .equ PORT_INT0IF_bm = 0x01 ; Pin 0 Interrupt Flag bit mask
        .equ PORT_INT0IF_bp = 0 ; Pin 0 Interrupt Flag bit position

        ; PORT_REMAP masks
        .equ PORT_USART0_bm = 0x10 ; Usart0 bit mask
        .equ PORT_USART0_bp = 4 ; Usart0 bit position
        .equ PORT_TC4D_bm = 0x08 ; Timer/Counter 4 Output Compare D bit mask
        .equ PORT_TC4D_bp = 3 ; Timer/Counter 4 Output Compare D bit position
        .equ PORT_TC4C_bm = 0x04 ; Timer/Counter 4 Output Compare C bit mask
        .equ PORT_TC4C_bp = 2 ; Timer/Counter 4 Output Compare C bit position
        .equ PORT_TC4B_bm = 0x02 ; Timer/Counter 4 Output Compare B bit mask
        .equ PORT_TC4B_bp = 1 ; Timer/Counter 4 Output Compare B bit position
        .equ PORT_TC4A_bm = 0x01 ; Timer/Counter 4 Output Compare A bit mask
        .equ PORT_TC4A_bp = 0 ; Timer/Counter 4 Output Compare A bit position

        ; PORT_PIN0CTRL masks
        .equ PORT_INVEN_bm = 0x40 ; Inverted I/O Enable bit mask
        .equ PORT_INVEN_bp = 6 ; Inverted I/O Enable bit position
        .equ PORT_OPC_gm = 0x38 ; Output/Pull Configuration group mask
        .equ PORT_OPC_gp = 3 ; Output/Pull Configuration group position
        .equ PORT_OPC0_bm = (1<<3) ; Output/Pull Configuration bit 0 mask
        .equ PORT_OPC0_bp = 3 ; Output/Pull Configuration bit 0 position
        .equ PORT_OPC1_bm = (1<<4) ; Output/Pull Configuration bit 1 mask
        .equ PORT_OPC1_bp = 4 ; Output/Pull Configuration bit 1 position
        .equ PORT_OPC2_bm = (1<<5) ; Output/Pull Configuration bit 2 mask
        .equ PORT_OPC2_bp = 5 ; Output/Pull Configuration bit 2 position
        .equ PORT_ISC_gm = 0x07 ; Input/Sense Configuration group mask
        .equ PORT_ISC_gp = 0 ; Input/Sense Configuration group position
        .equ PORT_ISC0_bm = (1<<0) ; Input/Sense Configuration bit 0 mask
        .equ PORT_ISC0_bp = 0 ; Input/Sense Configuration bit 0 position
        .equ PORT_ISC1_bm = (1<<1) ; Input/Sense Configuration bit 1 mask
        .equ PORT_ISC1_bp = 1 ; Input/Sense Configuration bit 1 position
        .equ PORT_ISC2_bm = (1<<2) ; Input/Sense Configuration bit 2 mask
        .equ PORT_ISC2_bp = 2 ; Input/Sense Configuration bit 2 position

        ; PORT_PIN1CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN2CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN3CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN4CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN5CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN6CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN7CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; Port Interrupt Level
        .equ PORT_INTLVL_OFF_gc = (0x00<<0) ; Interrupt Disabled
        .equ PORT_INTLVL_LO_gc = (0x01<<0) ; Low Level
        .equ PORT_INTLVL_MED_gc = (0x02<<0) ; Medium Level
        .equ PORT_INTLVL_HI_gc = (0x03<<0) ; High Level

        ; Output/Pull Configuration
        .equ PORT_OPC_TOTEM_gc = (0x00<<3) ; Totempole
        .equ PORT_OPC_BUSKEEPER_gc = (0x01<<3) ; Totempole w/ Bus keeper on Input and Output
        .equ PORT_OPC_PULLDOWN_gc = (0x02<<3) ; Totempole w/ Pull-down on Input
        .equ PORT_OPC_PULLUP_gc = (0x03<<3) ; Totempole w/ Pull-up on Input
        .equ PORT_OPC_WIREDOR_gc = (0x04<<3) ; Wired OR
        .equ PORT_OPC_WIREDAND_gc = (0x05<<3) ; Wired AND
        .equ PORT_OPC_WIREDORPULL_gc = (0x06<<3) ; Wired OR w/ Pull-down
        .equ PORT_OPC_WIREDANDPULL_gc = (0x07<<3) ; Wired AND w/ Pull-up

        ; Input/Sense Configuration
        .equ PORT_ISC_BOTHEDGES_gc = (0x00<<0) ; Sense Both Edges
        .equ PORT_ISC_RISING_gc = (0x01<<0) ; Sense Rising Edge
        .equ PORT_ISC_FALLING_gc = (0x02<<0) ; Sense Falling Edge
        .equ PORT_ISC_LEVEL_gc = (0x03<<0) ; Sense Level (Transparent For Events)
        .equ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0) ; Digital Input Buffer Forced Enable
        .equ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0) ; Disable Digital Input Buffer

0x0640 PORTC Port C

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	DIR	DIR[7:0]
0x0001	DIRSET	DIRSET[7:0]
0x0002	DIRCLR	DIRCLR[7:0]
0x0003	DIRTGL	DIRTGL[7:0]
0x0004	OUT	OUT[7:0]
0x0005	OUTSET	OUTSET[7:0]
0x0006	OUTCLR	OUTCLR[7:0]
0x0007	OUTTGL	OUTTGL[7:0]
0x0008	IN	IN[7:0]
0x0009	INTCTRL	-	-	-	-	-	-	INTLVL[1:0]
0x000A	INTMASK	INTMASK[7:0]
0x000B	Reserved	-	-	-	-	-	-	-	-
0x000C	INTFLAGS	INT7IF	INT6IF	INT5IF	INT4IF	INT3IF	INT2IF	INT1IF	INT0IF
0x000D	Reserved	-	-	-	-	-	-	-	-
0x000E	REMAP	-	-	-	USART0	TC4D	TC4C	TC4B	TC4A
0x0010	PIN0CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0011	PIN1CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0012	PIN2CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0013	PIN3CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0014	PIN4CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0015	PIN5CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0016	PIN6CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0017	PIN7CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0018	Reserved	-	-	-	-	-	-	-	-
0x0019	Reserved	-	-	-	-	-	-	-	-
0x0019	Reserved	-	-	-	-	-	-	-	-
0x001A	Reserved	-	-	-	-	-	-	-	-
0x001B	Reserved	-	-	-	-	-	-	-	-
0x001C	Reserved	-	-	-	-	-	-	-	-
0x001D	Reserved	-	-	-	-	-	-	-	-
0x001E	Reserved	-	-	-	-	-	-	-	-
0x001F	Reserved	-	-	-	-	-	-	-	-

Aliases

            
        ;*************************************************************************
        ;** PORTD - Port Configuration
        ;*************************************************************************
        
        .equ PORTD_DIR = 1632		// I/O Port Data Direction
        .equ PORTD_DIRSET = 1633		// I/O Port Data Direction Set
        .equ PORTD_DIRCLR = 1634		// I/O Port Data Direction Clear
        .equ PORTD_DIRTGL = 1635		// I/O Port Data Direction Toggle
        .equ PORTD_OUT = 1636		// I/O Port Output
        .equ PORTD_OUTSET = 1637		// I/O Port Output Set
        .equ PORTD_OUTCLR = 1638		// I/O Port Output Clear
        .equ PORTD_OUTTGL = 1639		// I/O Port Output Toggle
        .equ PORTD_IN = 1640		// I/O port Input
        .equ PORTD_INTCTRL = 1641		// Interrupt Control Register
        .equ PORTD_INTMASK = 1642		// Port Interrupt Mask
        .equ PORTD_INTFLAGS = 1644		// Interrupt Flag Register
        .equ PORTD_REMAP = 1646		// Pin Remap Register
        .equ PORTD_PIN0CTRL = 1648		// Pin 0 Control Register
        .equ PORTD_PIN1CTRL = 1649		// Pin 1 Control Register
        .equ PORTD_PIN2CTRL = 1650		// Pin 2 Control Register
        .equ PORTD_PIN3CTRL = 1651		// Pin 3 Control Register
        .equ PORTD_PIN4CTRL = 1652		// Pin 4 Control Register
        .equ PORTD_PIN5CTRL = 1653		// Pin 5 Control Register
        .equ PORTD_PIN6CTRL = 1654		// Pin 6 Control Register
                .equ PORTD_PIN7CTRL = 1655		// Pin 7 Control Register            
        ;*************************************************************************
        ;** PORT - Port Configuration
        ;*************************************************************************
        .equ PORT_DIR_offset = 0x00		// I/O Port Data Direction
        .equ PORT_DIRSET_offset = 0x01		// I/O Port Data Direction Set
        .equ PORT_DIRCLR_offset = 0x02		// I/O Port Data Direction Clear
        .equ PORT_DIRTGL_offset = 0x03		// I/O Port Data Direction Toggle
        .equ PORT_OUT_offset = 0x04		// I/O Port Output
        .equ PORT_OUTSET_offset = 0x05		// I/O Port Output Set
        .equ PORT_OUTCLR_offset = 0x06		// I/O Port Output Clear
        .equ PORT_OUTTGL_offset = 0x07		// I/O Port Output Toggle
        .equ PORT_IN_offset = 0x08		// I/O port Input
        .equ PORT_INTCTRL_offset = 0x09		// Interrupt Control Register
        .equ PORT_INTMASK_offset = 0x0A		// Port Interrupt Mask
        .equ PORT_INTFLAGS_offset = 0x0C		// Interrupt Flag Register
        .equ PORT_REMAP_offset = 0x0E		// Pin Remap Register
        .equ PORT_PIN0CTRL_offset = 0x10		// Pin 0 Control Register
        .equ PORT_PIN1CTRL_offset = 0x11		// Pin 1 Control Register
        .equ PORT_PIN2CTRL_offset = 0x12		// Pin 2 Control Register
        .equ PORT_PIN3CTRL_offset = 0x13		// Pin 3 Control Register
        .equ PORT_PIN4CTRL_offset = 0x14		// Pin 4 Control Register
        .equ PORT_PIN5CTRL_offset = 0x15		// Pin 5 Control Register
        .equ PORT_PIN6CTRL_offset = 0x16		// Pin 6 Control Register
        .equ PORT_PIN7CTRL_offset = 0x17		// Pin 7 Control Register
        ;*************************************************************************
        ;** PORT - Port Configuration
        ;*************************************************************************

        ; PORT_INTCTRL masks
        .equ PORT_INTLVL_gm = 0x03 ; Port Interrupt Level group mask
        .equ PORT_INTLVL_gp = 0 ; Port Interrupt Level group position
        .equ PORT_INTLVL0_bm = (1<<0) ; Port Interrupt Level bit 0 mask
        .equ PORT_INTLVL0_bp = 0 ; Port Interrupt Level bit 0 position
        .equ PORT_INTLVL1_bm = (1<<1) ; Port Interrupt Level bit 1 mask
        .equ PORT_INTLVL1_bp = 1 ; Port Interrupt Level bit 1 position

        ; PORT_INTFLAGS masks
        .equ PORT_INT7IF_bm = 0x80 ; Pin 7 Interrupt Flag bit mask
        .equ PORT_INT7IF_bp = 7 ; Pin 7 Interrupt Flag bit position
        .equ PORT_INT6IF_bm = 0x40 ; Pin 6 Interrupt Flag bit mask
        .equ PORT_INT6IF_bp = 6 ; Pin 6 Interrupt Flag bit position
        .equ PORT_INT5IF_bm = 0x20 ; Pin 5 Interrupt Flag bit mask
        .equ PORT_INT5IF_bp = 5 ; Pin 5 Interrupt Flag bit position
        .equ PORT_INT4IF_bm = 0x10 ; Pin 4 Interrupt Flag bit mask
        .equ PORT_INT4IF_bp = 4 ; Pin 4 Interrupt Flag bit position
        .equ PORT_INT3IF_bm = 0x08 ; Pin 3 Interrupt Flag bit mask
        .equ PORT_INT3IF_bp = 3 ; Pin 3 Interrupt Flag bit position
        .equ PORT_INT2IF_bm = 0x04 ; Pin 2 Interrupt Flag bit mask
        .equ PORT_INT2IF_bp = 2 ; Pin 2 Interrupt Flag bit position
        .equ PORT_INT1IF_bm = 0x02 ; Pin 1 Interrupt Flag bit mask
        .equ PORT_INT1IF_bp = 1 ; Pin 1 Interrupt Flag bit position
        .equ PORT_INT0IF_bm = 0x01 ; Pin 0 Interrupt Flag bit mask
        .equ PORT_INT0IF_bp = 0 ; Pin 0 Interrupt Flag bit position

        ; PORT_REMAP masks
        .equ PORT_USART0_bm = 0x10 ; Usart0 bit mask
        .equ PORT_USART0_bp = 4 ; Usart0 bit position
        .equ PORT_TC4D_bm = 0x08 ; Timer/Counter 4 Output Compare D bit mask
        .equ PORT_TC4D_bp = 3 ; Timer/Counter 4 Output Compare D bit position
        .equ PORT_TC4C_bm = 0x04 ; Timer/Counter 4 Output Compare C bit mask
        .equ PORT_TC4C_bp = 2 ; Timer/Counter 4 Output Compare C bit position
        .equ PORT_TC4B_bm = 0x02 ; Timer/Counter 4 Output Compare B bit mask
        .equ PORT_TC4B_bp = 1 ; Timer/Counter 4 Output Compare B bit position
        .equ PORT_TC4A_bm = 0x01 ; Timer/Counter 4 Output Compare A bit mask
        .equ PORT_TC4A_bp = 0 ; Timer/Counter 4 Output Compare A bit position

        ; PORT_PIN0CTRL masks
        .equ PORT_INVEN_bm = 0x40 ; Inverted I/O Enable bit mask
        .equ PORT_INVEN_bp = 6 ; Inverted I/O Enable bit position
        .equ PORT_OPC_gm = 0x38 ; Output/Pull Configuration group mask
        .equ PORT_OPC_gp = 3 ; Output/Pull Configuration group position
        .equ PORT_OPC0_bm = (1<<3) ; Output/Pull Configuration bit 0 mask
        .equ PORT_OPC0_bp = 3 ; Output/Pull Configuration bit 0 position
        .equ PORT_OPC1_bm = (1<<4) ; Output/Pull Configuration bit 1 mask
        .equ PORT_OPC1_bp = 4 ; Output/Pull Configuration bit 1 position
        .equ PORT_OPC2_bm = (1<<5) ; Output/Pull Configuration bit 2 mask
        .equ PORT_OPC2_bp = 5 ; Output/Pull Configuration bit 2 position
        .equ PORT_ISC_gm = 0x07 ; Input/Sense Configuration group mask
        .equ PORT_ISC_gp = 0 ; Input/Sense Configuration group position
        .equ PORT_ISC0_bm = (1<<0) ; Input/Sense Configuration bit 0 mask
        .equ PORT_ISC0_bp = 0 ; Input/Sense Configuration bit 0 position
        .equ PORT_ISC1_bm = (1<<1) ; Input/Sense Configuration bit 1 mask
        .equ PORT_ISC1_bp = 1 ; Input/Sense Configuration bit 1 position
        .equ PORT_ISC2_bm = (1<<2) ; Input/Sense Configuration bit 2 mask
        .equ PORT_ISC2_bp = 2 ; Input/Sense Configuration bit 2 position

        ; PORT_PIN1CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN2CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN3CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN4CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN5CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN6CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN7CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; Port Interrupt Level
        .equ PORT_INTLVL_OFF_gc = (0x00<<0) ; Interrupt Disabled
        .equ PORT_INTLVL_LO_gc = (0x01<<0) ; Low Level
        .equ PORT_INTLVL_MED_gc = (0x02<<0) ; Medium Level
        .equ PORT_INTLVL_HI_gc = (0x03<<0) ; High Level

        ; Output/Pull Configuration
        .equ PORT_OPC_TOTEM_gc = (0x00<<3) ; Totempole
        .equ PORT_OPC_BUSKEEPER_gc = (0x01<<3) ; Totempole w/ Bus keeper on Input and Output
        .equ PORT_OPC_PULLDOWN_gc = (0x02<<3) ; Totempole w/ Pull-down on Input
        .equ PORT_OPC_PULLUP_gc = (0x03<<3) ; Totempole w/ Pull-up on Input
        .equ PORT_OPC_WIREDOR_gc = (0x04<<3) ; Wired OR
        .equ PORT_OPC_WIREDAND_gc = (0x05<<3) ; Wired AND
        .equ PORT_OPC_WIREDORPULL_gc = (0x06<<3) ; Wired OR w/ Pull-down
        .equ PORT_OPC_WIREDANDPULL_gc = (0x07<<3) ; Wired AND w/ Pull-up

        ; Input/Sense Configuration
        .equ PORT_ISC_BOTHEDGES_gc = (0x00<<0) ; Sense Both Edges
        .equ PORT_ISC_RISING_gc = (0x01<<0) ; Sense Rising Edge
        .equ PORT_ISC_FALLING_gc = (0x02<<0) ; Sense Falling Edge
        .equ PORT_ISC_LEVEL_gc = (0x03<<0) ; Sense Level (Transparent For Events)
        .equ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0) ; Digital Input Buffer Forced Enable
        .equ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0) ; Disable Digital Input Buffer

0x0660 PORTD Port D

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	DIR	DIR[7:0]
0x0001	DIRSET	DIRSET[7:0]
0x0002	DIRCLR	DIRCLR[7:0]
0x0003	DIRTGL	DIRTGL[7:0]
0x0004	OUT	OUT[7:0]
0x0005	OUTSET	OUTSET[7:0]
0x0006	OUTCLR	OUTCLR[7:0]
0x0007	OUTTGL	OUTTGL[7:0]
0x0008	IN	IN[7:0]
0x0009	INTCTRL	-	-	-	-	-	-	INTLVL[1:0]
0x000A	INTMASK	INTMASK[7:0]
0x000B	Reserved	-	-	-	-	-	-	-	-
0x000C	INTFLAGS	INT7IF	INT6IF	INT5IF	INT4IF	INT3IF	INT2IF	INT1IF	INT0IF
0x000D	Reserved	-	-	-	-	-	-	-	-
0x000E	REMAP	-	-	-	USART0	TC4D	TC4C	TC4B	TC4A
0x0010	PIN0CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0011	PIN1CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0012	PIN2CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0013	PIN3CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0014	PIN4CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0015	PIN5CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0016	PIN6CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0017	PIN7CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0018	Reserved	-	-	-	-	-	-	-	-
0x0019	Reserved	-	-	-	-	-	-	-	-
0x0019	Reserved	-	-	-	-	-	-	-	-
0x001A	Reserved	-	-	-	-	-	-	-	-
0x001B	Reserved	-	-	-	-	-	-	-	-
0x001C	Reserved	-	-	-	-	-	-	-	-
0x001D	Reserved	-	-	-	-	-	-	-	-
0x001E	Reserved	-	-	-	-	-	-	-	-
0x001F	Reserved	-	-	-	-	-	-	-	-

Aliases

            
        ;*************************************************************************
        ;** PORTR - Port Configuration
        ;*************************************************************************
        
        .equ PORTR_DIR = 2016		// I/O Port Data Direction
        .equ PORTR_DIRSET = 2017		// I/O Port Data Direction Set
        .equ PORTR_DIRCLR = 2018		// I/O Port Data Direction Clear
        .equ PORTR_DIRTGL = 2019		// I/O Port Data Direction Toggle
        .equ PORTR_OUT = 2020		// I/O Port Output
        .equ PORTR_OUTSET = 2021		// I/O Port Output Set
        .equ PORTR_OUTCLR = 2022		// I/O Port Output Clear
        .equ PORTR_OUTTGL = 2023		// I/O Port Output Toggle
        .equ PORTR_IN = 2024		// I/O port Input
        .equ PORTR_INTCTRL = 2025		// Interrupt Control Register
        .equ PORTR_INTMASK = 2026		// Port Interrupt Mask
        .equ PORTR_INTFLAGS = 2028		// Interrupt Flag Register
        .equ PORTR_REMAP = 2030		// Pin Remap Register
        .equ PORTR_PIN0CTRL = 2032		// Pin 0 Control Register
        .equ PORTR_PIN1CTRL = 2033		// Pin 1 Control Register
        .equ PORTR_PIN2CTRL = 2034		// Pin 2 Control Register
        .equ PORTR_PIN3CTRL = 2035		// Pin 3 Control Register
        .equ PORTR_PIN4CTRL = 2036		// Pin 4 Control Register
        .equ PORTR_PIN5CTRL = 2037		// Pin 5 Control Register
        .equ PORTR_PIN6CTRL = 2038		// Pin 6 Control Register
        .equ PORTR_PIN7CTRL = 2039		// Pin 7 Control Register        
        ;*************************************************************************
        ;** PORT - Port Configuration
        ;*************************************************************************
        .equ PORT_DIR_offset = 0x00		// I/O Port Data Direction
        .equ PORT_DIRSET_offset = 0x01		// I/O Port Data Direction Set
        .equ PORT_DIRCLR_offset = 0x02		// I/O Port Data Direction Clear
        .equ PORT_DIRTGL_offset = 0x03		// I/O Port Data Direction Toggle
        .equ PORT_OUT_offset = 0x04		// I/O Port Output
        .equ PORT_OUTSET_offset = 0x05		// I/O Port Output Set
        .equ PORT_OUTCLR_offset = 0x06		// I/O Port Output Clear
        .equ PORT_OUTTGL_offset = 0x07		// I/O Port Output Toggle
        .equ PORT_IN_offset = 0x08		// I/O port Input
        .equ PORT_INTCTRL_offset = 0x09		// Interrupt Control Register
        .equ PORT_INTMASK_offset = 0x0A		// Port Interrupt Mask
        .equ PORT_INTFLAGS_offset = 0x0C		// Interrupt Flag Register
        .equ PORT_REMAP_offset = 0x0E		// Pin Remap Register
        .equ PORT_PIN0CTRL_offset = 0x10		// Pin 0 Control Register
        .equ PORT_PIN1CTRL_offset = 0x11		// Pin 1 Control Register
        .equ PORT_PIN2CTRL_offset = 0x12		// Pin 2 Control Register
        .equ PORT_PIN3CTRL_offset = 0x13		// Pin 3 Control Register
        .equ PORT_PIN4CTRL_offset = 0x14		// Pin 4 Control Register
        .equ PORT_PIN5CTRL_offset = 0x15		// Pin 5 Control Register
        .equ PORT_PIN6CTRL_offset = 0x16		// Pin 6 Control Register
        .equ PORT_PIN7CTRL_offset = 0x17		// Pin 7 Control Register
        ;*************************************************************************
        ;** PORT - Port Configuration
        ;*************************************************************************

        ; PORT_INTCTRL masks
        .equ PORT_INTLVL_gm = 0x03 ; Port Interrupt Level group mask
        .equ PORT_INTLVL_gp = 0 ; Port Interrupt Level group position
        .equ PORT_INTLVL0_bm = (1<<0) ; Port Interrupt Level bit 0 mask
        .equ PORT_INTLVL0_bp = 0 ; Port Interrupt Level bit 0 position
        .equ PORT_INTLVL1_bm = (1<<1) ; Port Interrupt Level bit 1 mask
        .equ PORT_INTLVL1_bp = 1 ; Port Interrupt Level bit 1 position

        ; PORT_INTFLAGS masks
        .equ PORT_INT7IF_bm = 0x80 ; Pin 7 Interrupt Flag bit mask
        .equ PORT_INT7IF_bp = 7 ; Pin 7 Interrupt Flag bit position
        .equ PORT_INT6IF_bm = 0x40 ; Pin 6 Interrupt Flag bit mask
        .equ PORT_INT6IF_bp = 6 ; Pin 6 Interrupt Flag bit position
        .equ PORT_INT5IF_bm = 0x20 ; Pin 5 Interrupt Flag bit mask
        .equ PORT_INT5IF_bp = 5 ; Pin 5 Interrupt Flag bit position
        .equ PORT_INT4IF_bm = 0x10 ; Pin 4 Interrupt Flag bit mask
        .equ PORT_INT4IF_bp = 4 ; Pin 4 Interrupt Flag bit position
        .equ PORT_INT3IF_bm = 0x08 ; Pin 3 Interrupt Flag bit mask
        .equ PORT_INT3IF_bp = 3 ; Pin 3 Interrupt Flag bit position
        .equ PORT_INT2IF_bm = 0x04 ; Pin 2 Interrupt Flag bit mask
        .equ PORT_INT2IF_bp = 2 ; Pin 2 Interrupt Flag bit position
        .equ PORT_INT1IF_bm = 0x02 ; Pin 1 Interrupt Flag bit mask
        .equ PORT_INT1IF_bp = 1 ; Pin 1 Interrupt Flag bit position
        .equ PORT_INT0IF_bm = 0x01 ; Pin 0 Interrupt Flag bit mask
        .equ PORT_INT0IF_bp = 0 ; Pin 0 Interrupt Flag bit position

        ; PORT_REMAP masks
        .equ PORT_USART0_bm = 0x10 ; Usart0 bit mask
        .equ PORT_USART0_bp = 4 ; Usart0 bit position
        .equ PORT_TC4D_bm = 0x08 ; Timer/Counter 4 Output Compare D bit mask
        .equ PORT_TC4D_bp = 3 ; Timer/Counter 4 Output Compare D bit position
        .equ PORT_TC4C_bm = 0x04 ; Timer/Counter 4 Output Compare C bit mask
        .equ PORT_TC4C_bp = 2 ; Timer/Counter 4 Output Compare C bit position
        .equ PORT_TC4B_bm = 0x02 ; Timer/Counter 4 Output Compare B bit mask
        .equ PORT_TC4B_bp = 1 ; Timer/Counter 4 Output Compare B bit position
        .equ PORT_TC4A_bm = 0x01 ; Timer/Counter 4 Output Compare A bit mask
        .equ PORT_TC4A_bp = 0 ; Timer/Counter 4 Output Compare A bit position

        ; PORT_PIN0CTRL masks
        .equ PORT_INVEN_bm = 0x40 ; Inverted I/O Enable bit mask
        .equ PORT_INVEN_bp = 6 ; Inverted I/O Enable bit position
        .equ PORT_OPC_gm = 0x38 ; Output/Pull Configuration group mask
        .equ PORT_OPC_gp = 3 ; Output/Pull Configuration group position
        .equ PORT_OPC0_bm = (1<<3) ; Output/Pull Configuration bit 0 mask
        .equ PORT_OPC0_bp = 3 ; Output/Pull Configuration bit 0 position
        .equ PORT_OPC1_bm = (1<<4) ; Output/Pull Configuration bit 1 mask
        .equ PORT_OPC1_bp = 4 ; Output/Pull Configuration bit 1 position
        .equ PORT_OPC2_bm = (1<<5) ; Output/Pull Configuration bit 2 mask
        .equ PORT_OPC2_bp = 5 ; Output/Pull Configuration bit 2 position
        .equ PORT_ISC_gm = 0x07 ; Input/Sense Configuration group mask
        .equ PORT_ISC_gp = 0 ; Input/Sense Configuration group position
        .equ PORT_ISC0_bm = (1<<0) ; Input/Sense Configuration bit 0 mask
        .equ PORT_ISC0_bp = 0 ; Input/Sense Configuration bit 0 position
        .equ PORT_ISC1_bm = (1<<1) ; Input/Sense Configuration bit 1 mask
        .equ PORT_ISC1_bp = 1 ; Input/Sense Configuration bit 1 position
        .equ PORT_ISC2_bm = (1<<2) ; Input/Sense Configuration bit 2 mask
        .equ PORT_ISC2_bp = 2 ; Input/Sense Configuration bit 2 position

        ; PORT_PIN1CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN2CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN3CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN4CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN5CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN6CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; PORT_PIN7CTRL masks
        ; Masks for PORT_INVEN already defined
        ; Masks for PORT_OPC already defined
        ; Masks for PORT_ISC already defined

        ; Port Interrupt Level
        .equ PORT_INTLVL_OFF_gc = (0x00<<0) ; Interrupt Disabled
        .equ PORT_INTLVL_LO_gc = (0x01<<0) ; Low Level
        .equ PORT_INTLVL_MED_gc = (0x02<<0) ; Medium Level
        .equ PORT_INTLVL_HI_gc = (0x03<<0) ; High Level

        ; Output/Pull Configuration
        .equ PORT_OPC_TOTEM_gc = (0x00<<3) ; Totempole
        .equ PORT_OPC_BUSKEEPER_gc = (0x01<<3) ; Totempole w/ Bus keeper on Input and Output
        .equ PORT_OPC_PULLDOWN_gc = (0x02<<3) ; Totempole w/ Pull-down on Input
        .equ PORT_OPC_PULLUP_gc = (0x03<<3) ; Totempole w/ Pull-up on Input
        .equ PORT_OPC_WIREDOR_gc = (0x04<<3) ; Wired OR
        .equ PORT_OPC_WIREDAND_gc = (0x05<<3) ; Wired AND
        .equ PORT_OPC_WIREDORPULL_gc = (0x06<<3) ; Wired OR w/ Pull-down
        .equ PORT_OPC_WIREDANDPULL_gc = (0x07<<3) ; Wired AND w/ Pull-up

        ; Input/Sense Configuration
        .equ PORT_ISC_BOTHEDGES_gc = (0x00<<0) ; Sense Both Edges
        .equ PORT_ISC_RISING_gc = (0x01<<0) ; Sense Rising Edge
        .equ PORT_ISC_FALLING_gc = (0x02<<0) ; Sense Falling Edge
        .equ PORT_ISC_LEVEL_gc = (0x03<<0) ; Sense Level (Transparent For Events)
        .equ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0) ; Digital Input Buffer Forced Enable
        .equ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0) ; Disable Digital Input Buffer

0x07E0 PORTR Port R

Offset	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0000	DIR	DIR[7:0]
0x0001	DIRSET	DIRSET[7:0]
0x0002	DIRCLR	DIRCLR[7:0]
0x0003	DIRTGL	DIRTGL[7:0]
0x0004	OUT	OUT[7:0]
0x0005	OUTSET	OUTSET[7:0]
0x0006	OUTCLR	OUTCLR[7:0]
0x0007	OUTTGL	OUTTGL[7:0]
0x0008	IN	IN[7:0]
0x0009	INTCTRL	-	-	-	-	-	-	INTLVL[1:0]
0x000A	INTMASK	INTMASK[7:0]
0x000B	Reserved	-	-	-	-	-	-	-	-
0x000C	INTFLAGS	INT7IF	INT6IF	INT5IF	INT4IF	INT3IF	INT2IF	INT1IF	INT0IF
0x000D	Reserved	-	-	-	-	-	-	-	-
0x000E	REMAP	-	-	-	USART0	TC4D	TC4C	TC4B	TC4A
0x0010	PIN0CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0011	PIN1CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0012	PIN2CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0013	PIN3CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0014	PIN4CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0015	PIN5CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0016	PIN6CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0017	PIN7CTRL	-	INVEN	OPC[2:0]			ISC[2:0]
0x0018	Reserved	-	-	-	-	-	-	-	-
0x0019	Reserved	-	-	-	-	-	-	-	-
0x0019	Reserved	-	-	-	-	-	-	-	-
0x001A	Reserved	-	-	-	-	-	-	-	-
0x001B	Reserved	-	-	-	-	-	-	-	-
0x001C	Reserved	-	-	-	-	-	-	-	-
0x001D	Reserved	-	-	-	-	-	-	-	-
0x001E	Reserved	-	-	-	-	-	-	-	-
0x001F	Reserved	-	-	-	-	-	-	-	-